* [PATCH 0/2] clk: renesas: r8a779h0: Add FCPVX and VSPX clocks @ 2025-01-15 17:59 Niklas Söderlund 2025-01-15 17:59 ` [PATCH 1/2] clk: renesas: r8a779h0: Add FCPVX clock Niklas Söderlund 2025-01-15 17:59 ` [PATCH 2/2] clk: renesas: r8a779h0: Add VSPX clock Niklas Söderlund 0 siblings, 2 replies; 6+ messages in thread From: Niklas Söderlund @ 2025-01-15 17:59 UTC (permalink / raw) To: Geert Uytterhoeven, linux-renesas-soc, linux-clk; +Cc: Niklas Söderlund Hi Geert, This series adds the missing FCPVX and VSPX clocks. Hopefully this will be the last clock series needed to enable these clocks on all Gen4 SoCs. Niklas Söderlund (2): clk: renesas: r8a779h0: Add FCPVX clock clk: renesas: r8a779h0: Add VSPX clock drivers/clk/renesas/r8a779h0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.48.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] clk: renesas: r8a779h0: Add FCPVX clock 2025-01-15 17:59 [PATCH 0/2] clk: renesas: r8a779h0: Add FCPVX and VSPX clocks Niklas Söderlund @ 2025-01-15 17:59 ` Niklas Söderlund 2025-01-17 16:29 ` Geert Uytterhoeven 2025-01-15 17:59 ` [PATCH 2/2] clk: renesas: r8a779h0: Add VSPX clock Niklas Söderlund 1 sibling, 1 reply; 6+ messages in thread From: Niklas Söderlund @ 2025-01-15 17:59 UTC (permalink / raw) To: Geert Uytterhoeven, linux-renesas-soc, linux-clk; +Cc: Niklas Söderlund Add the FCPVX modules clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 4c8052ac32df..b92990f5ec44 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -239,6 +239,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), + DEF_MOD("fcpvx0", 1100, R8A779H0_CLK_S0D4_VIO), DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER), DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER), }; -- 2.48.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] clk: renesas: r8a779h0: Add FCPVX clock 2025-01-15 17:59 ` [PATCH 1/2] clk: renesas: r8a779h0: Add FCPVX clock Niklas Söderlund @ 2025-01-17 16:29 ` Geert Uytterhoeven 2025-01-17 16:44 ` Niklas Söderlund 0 siblings, 1 reply; 6+ messages in thread From: Geert Uytterhoeven @ 2025-01-17 16:29 UTC (permalink / raw) To: Niklas Söderlund; +Cc: linux-renesas-soc, linux-clk Hi Niklas, On Wed, Jan 15, 2025 at 6:59 PM Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> wrote: > Add the FCPVX modules clock for Renesas R-Car V4M. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Thanks for your patch! Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk for v6.15. > --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > @@ -239,6 +239,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), > DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), > DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), > + DEF_MOD("fcpvx0", 1100, R8A779H0_CLK_S0D4_VIO), Any specific reason you are not using S0D1, like on R-Car V4H? I can update this while applying. > DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER), > DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER), Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] clk: renesas: r8a779h0: Add FCPVX clock 2025-01-17 16:29 ` Geert Uytterhoeven @ 2025-01-17 16:44 ` Niklas Söderlund 0 siblings, 0 replies; 6+ messages in thread From: Niklas Söderlund @ 2025-01-17 16:44 UTC (permalink / raw) To: Geert Uytterhoeven; +Cc: linux-renesas-soc, linux-clk Hello Geert, Thanks for your feedback. On 2025-01-17 17:29:21 +0100, Geert Uytterhoeven wrote: > Hi Niklas, > > On Wed, Jan 15, 2025 at 6:59 PM Niklas Söderlund > <niklas.soderlund+renesas@ragnatech.se> wrote: > > Add the FCPVX modules clock for Renesas R-Car V4M. > > > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > > Thanks for your patch! > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will queue in renesas-clk for v6.15. > > > --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > > @@ -239,6 +239,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > > DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), > > DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), > > DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), > > + DEF_MOD("fcpvx0", 1100, R8A779H0_CLK_S0D4_VIO), > > Any specific reason you are not using S0D1, like on R-Car V4H? > I can update this while applying. Nice catch it should be S0D1. I picked it since it listed both FCPVX and VSPX, and I compared it to S0D2 which only lists FCPVX. Checking the datasheet again now after your feedback I see indeed S0D1 also lists both FCPVX and VSPX. Thanks for fixing this while applying, same comment for 2/2. > > > DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER), > > DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER), > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds -- Kind Regards, Niklas Söderlund ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] clk: renesas: r8a779h0: Add VSPX clock 2025-01-15 17:59 [PATCH 0/2] clk: renesas: r8a779h0: Add FCPVX and VSPX clocks Niklas Söderlund 2025-01-15 17:59 ` [PATCH 1/2] clk: renesas: r8a779h0: Add FCPVX clock Niklas Söderlund @ 2025-01-15 17:59 ` Niklas Söderlund 2025-01-17 16:30 ` Geert Uytterhoeven 1 sibling, 1 reply; 6+ messages in thread From: Niklas Söderlund @ 2025-01-15 17:59 UTC (permalink / raw) To: Geert Uytterhoeven, linux-renesas-soc, linux-clk; +Cc: Niklas Söderlund Add the VSPX modules clock for Renesas R-Car V4M. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index b92990f5ec44..22b0af0dbb27 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -239,6 +239,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), + DEF_MOD("vspx0", 1028, R8A779H0_CLK_S0D4_VIO), DEF_MOD("fcpvx0", 1100, R8A779H0_CLK_S0D4_VIO), DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER), DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER), -- 2.48.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] clk: renesas: r8a779h0: Add VSPX clock 2025-01-15 17:59 ` [PATCH 2/2] clk: renesas: r8a779h0: Add VSPX clock Niklas Söderlund @ 2025-01-17 16:30 ` Geert Uytterhoeven 0 siblings, 0 replies; 6+ messages in thread From: Geert Uytterhoeven @ 2025-01-17 16:30 UTC (permalink / raw) To: Niklas Söderlund; +Cc: linux-renesas-soc, linux-clk Hi Niklas, On Wed, Jan 15, 2025 at 6:59 PM Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> wrote: > Add the VSPX modules clock for Renesas R-Car V4M. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Thanks for your patch! Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk for v6.15. > --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > @@ -239,6 +239,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), > DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), > DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), > + DEF_MOD("vspx0", 1028, R8A779H0_CLK_S0D4_VIO), Any specific reason you are not using S0D1, like on R-Car V4H? I can update this while applying. > DEF_MOD("fcpvx0", 1100, R8A779H0_CLK_S0D4_VIO), > DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER), > DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER), Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-01-17 16:44 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-01-15 17:59 [PATCH 0/2] clk: renesas: r8a779h0: Add FCPVX and VSPX clocks Niklas Söderlund 2025-01-15 17:59 ` [PATCH 1/2] clk: renesas: r8a779h0: Add FCPVX clock Niklas Söderlund 2025-01-17 16:29 ` Geert Uytterhoeven 2025-01-17 16:44 ` Niklas Söderlund 2025-01-15 17:59 ` [PATCH 2/2] clk: renesas: r8a779h0: Add VSPX clock Niklas Söderlund 2025-01-17 16:30 ` Geert Uytterhoeven
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