* [PATCH] arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order
@ 2022-07-04 16:16 Geert Uytterhoeven
2022-07-11 15:32 ` Wolfram Sang
0 siblings, 1 reply; 2+ messages in thread
From: Geert Uytterhoeven @ 2022-07-04 16:16 UTC (permalink / raw)
To: Magnus Damm; +Cc: Wolfram Sang, linux-renesas-soc, Geert Uytterhoeven
The scif0 nodes were accidentally inserted after the scif3 nodes,
breaking alphabetical sort order.
Fixes: 1614c8624a48b9c9 ("arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in renesas-devel for v5.20.
.../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
index 7fa225dafa6e5749..2cc365a720c19fc5 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -55,16 +55,16 @@ i2c4_pins: i2c4 {
function = "i2c4";
};
- scif3_pins: scif3 {
- groups = "scif3_data", "scif3_ctrl";
- function = "scif3";
- };
-
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";
};
+ scif3_pins: scif3 {
+ groups = "scif3_data", "scif3_ctrl";
+ function = "scif3";
+ };
+
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
@@ -76,16 +76,16 @@ &rwdt {
status = "okay";
};
-&scif3 {
- pinctrl-0 = <&scif3_pins>;
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
-&scif0 {
- pinctrl-0 = <&scif0_pins>;
+&scif3 {
+ pinctrl-0 = <&scif3_pins>;
pinctrl-names = "default";
uart-has-rtscts;
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order
2022-07-04 16:16 [PATCH] arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order Geert Uytterhoeven
@ 2022-07-11 15:32 ` Wolfram Sang
0 siblings, 0 replies; 2+ messages in thread
From: Wolfram Sang @ 2022-07-11 15:32 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Magnus Damm, linux-renesas-soc
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On Mon, Jul 04, 2022 at 06:16:26PM +0200, Geert Uytterhoeven wrote:
> The scif0 nodes were accidentally inserted after the scif3 nodes,
> breaking alphabetical sort order.
>
> Fixes: 1614c8624a48b9c9 ("arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
I can't test because my board fails to boot with renesas-drivers for
other reasons. The patch looks good, however, so:
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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