[PATCH RFT 0/6] PWM & TPU patches for V4M

[PATCH RFT 0/6] PWM & TPU patches for V4M

[Wolfram Sang]

Here are the patches I prepared to enable PWM and TPU on the R-Car V4M
SoC. Only patches 1-4 are for upstream, the rest are convenience patches
for testers. They are based on linus-git as of today.

As discussed privately, Geert wants to have a try testing these. I
cannot because testing needs physical access to HW which I don't have.
Thanks, Geert!


Cong Dang (2):
  clk: renesas: r8a779h0: Add PWM clock
  clk: renesas: r8a779h0: Add TPU clock

Khanh Le (1):
  arm64: dts: renesas: r8a779h0: Add PWM device node

Wolfram Sang (3):
  arm64: dts: renesas: r8a779h0: Add TPU device node
  arm64: dts: r8a779h0-gray-hawk-single: Add PWM support
  arm64: dts: r8a779h0-gray-hawk-single: Add TPU support

 .../dts/renesas/r8a779h0-gray-hawk-single.dts | 36 +++++++++++
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi     | 61 +++++++++++++++++++
 drivers/clk/renesas/r8a779h0-cpg-mssr.c       |  2 +
 3 files changed, 99 insertions(+)

-- 
2.43.0

[PATCH RFT 1/6] clk: renesas: r8a779h0: Add PWM clock

[Wolfram Sang]

From: Cong Dang <cong.dang.xn@renesas.com>

Add the module clock used by the PWM timers on the Renesas R-Car V4M
(R8A779H0) SoC.

Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
[wsa: rebased]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index 16a2e26abcc7..a9614d0c51ae 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -195,6 +195,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
 	DEF_MOD("msi3",		621,	R8A779H0_CLK_MSO),
 	DEF_MOD("msi4",		622,	R8A779H0_CLK_MSO),
 	DEF_MOD("msi5",		623,	R8A779H0_CLK_MSO),
+	DEF_MOD("pwm",		628,	R8A779H0_CLK_SASYNCPERD4),
 	DEF_MOD("rpc-if",	629,	R8A779H0_CLK_RPCD2),
 	DEF_MOD("scif0",	702,	R8A779H0_CLK_SASYNCPERD4),
 	DEF_MOD("scif1",	703,	R8A779H0_CLK_SASYNCPERD4),
-- 
2.43.0

Re: [PATCH RFT 1/6] clk: renesas: r8a779h0: Add PWM clock

[Geert Uytterhoeven]

On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Cong Dang <cong.dang.xn@renesas.com>
>
> Add the module clock used by the PWM timers on the Renesas R-Car V4M
> (R8A779H0) SoC.
>
> Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
> [wsa: rebased]
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.12.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH RFT 2/6] clk: renesas: r8a779h0: Add TPU clock

[Wolfram Sang]

From: Cong Dang <cong.dang.xn@renesas.com>

Add the module clock used by the 16-Bit Timer Pulse Unit (TPU) on the
Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
[wsa: rebased]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index a9614d0c51ae..1f311206506d 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -209,6 +209,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
 	DEF_MOD("tmu2",		715,	R8A779H0_CLK_SASYNCPERD2),
 	DEF_MOD("tmu3",		716,	R8A779H0_CLK_SASYNCPERD2),
 	DEF_MOD("tmu4",		717,	R8A779H0_CLK_SASYNCPERD2),
+	DEF_MOD("tpu0",		718,	R8A779H0_CLK_SASYNCPERD4),
 	DEF_MOD("vin00",	730,	R8A779H0_CLK_S0D4_VIO),
 	DEF_MOD("vin01",	731,	R8A779H0_CLK_S0D4_VIO),
 	DEF_MOD("vin02",	800,	R8A779H0_CLK_S0D4_VIO),
-- 
2.43.0

Re: [PATCH RFT 2/6] clk: renesas: r8a779h0: Add TPU clock

[Geert Uytterhoeven]

On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Cong Dang <cong.dang.xn@renesas.com>
>
> Add the module clock used by the 16-Bit Timer Pulse Unit (TPU) on the
> Renesas R-Car V4M (R8A779H0) SoC.
>
> Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
> [wsa: rebased]
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.12.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH RFT 2/6] clk: renesas: r8a779h0: Add TPU clock

[Geert Uytterhoeven]

On Mon, Jul 29, 2024 at 8:39 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
> <wsa+renesas@sang-engineering.com> wrote:
> > From: Cong Dang <cong.dang.xn@renesas.com>
> >
> > Add the module clock used by the 16-Bit Timer Pulse Unit (TPU) on the
> > Renesas R-Car V4M (R8A779H0) SoC.
> >
> > Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
> > [wsa: rebased]
> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-clk for v6.12.

Postponing this until it works.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH RFT 3/6] arm64: dts: renesas: r8a779h0: Add PWM device node

[Wolfram Sang]

From: Khanh Le <khanh.le.xr@renesas.com>

This patch adds device tree support for PWM/TPU on R-Car V4M (R8A779H0).

Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
[wsa: rebased, dropped TPU part to be upstreamed seperately]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 50 +++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index a03ab2b6a859..000ea93d65e5 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@ -781,6 +781,56 @@ avb2: ethernet@e6820000 {
 			status = "disabled";
 		};
 
+		pwm0: pwm@e6e30000 {
+			compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar";
+			reg = <0 0xe6e30000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 628>;
+			power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+			resets = <&cpg 628>;
+			status = "disabled";
+		};
+
+		pwm1: pwm@e6e31000 {
+			compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar";
+			reg = <0 0xe6e31000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 628>;
+			power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+			resets = <&cpg 628>;
+			status = "disabled";
+		};
+
+		pwm2: pwm@e6e32000 {
+			compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar";
+			reg = <0 0xe6e32000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 628>;
+			power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+			resets = <&cpg 628>;
+			status = "disabled";
+		};
+
+		pwm3: pwm@e6e33000 {
+			compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar";
+			reg = <0 0xe6e33000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 628>;
+			power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+			resets = <&cpg 628>;
+			status = "disabled";
+		};
+
+		pwm4: pwm@e6e34000 {
+			compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar";
+			reg = <0 0xe6e34000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 628>;
+			power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+			resets = <&cpg 628>;
+			status = "disabled";
+		};
+
 		scif0: serial@e6e60000 {
 			compatible = "renesas,scif-r8a779h0",
 				     "renesas,rcar-gen4-scif", "renesas,scif";
-- 
2.43.0

Re: [PATCH RFT 3/6] arm64: dts: renesas: r8a779h0: Add PWM device node

[Geert Uytterhoeven]

On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Khanh Le <khanh.le.xr@renesas.com>
>
> This patch adds device tree support for PWM/TPU on R-Car V4M (R8A779H0).

Dropping TPU...

>
> Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
> [wsa: rebased, dropped TPU part to be upstreamed seperately]
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.12 with the above fixed.

PWM1 and PWM2 are working fine, so
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH RFT 3/6] arm64: dts: renesas: r8a779h0: Add PWM device node

[Wolfram Sang]

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> > This patch adds device tree support for PWM/TPU on R-Car V4M (R8A779H0).
> 
> Dropping TPU...

Oops, right. Thank you...

> PWM1 and PWM2 are working fine, so
> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>

... and thank you for testing this locally!


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[PATCH RFT 4/6] arm64: dts: renesas: r8a779h0: Add TPU device node

[Wolfram Sang]

Add a device node for the 16-Bit Timer Pulse Unit (TPU) on the Renesas
R-Car V4H (R8A779G0) SoC.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index 000ea93d65e5..e12935eafff3 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@ -1023,6 +1023,17 @@ vin00isp0: endpoint@0 {
 			};
 		};
 
+		tpu: pwm@e6e80000 {
+			compatible = "renesas,tpu-r8a779h0", "renesas,tpu";
+			reg = <0 0xe6e80000 0 0x148>;
+			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 718>;
+			power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+			resets = <&cpg 718>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		vin01: video@e6ef1000 {
 			compatible = "renesas,vin-r8a779h0";
 			reg = <0 0xe6ef1000 0 0x1000>;
-- 
2.43.0

Re: [PATCH RFT 4/6] arm64: dts: renesas: r8a779h0: Add TPU device node

[Geert Uytterhoeven]

On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Add a device node for the 16-Bit Timer Pulse Unit (TPU) on the Renesas
> R-Car V4H (R8A779G0) SoC.

R8A779H0

>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> index 000ea93d65e5..e12935eafff3 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> @@ -1023,6 +1023,17 @@ vin00isp0: endpoint@0 {
>                         };
>                 };
>
> +               tpu: pwm@e6e80000 {

Move before spi@e6e90000...

> +                       compatible = "renesas,tpu-r8a779h0", "renesas,tpu";
> +                       reg = <0 0xe6e80000 0 0x148>;
> +                       interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD 718>;
> +                       power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
> +                       resets = <&cpg 718>;
> +                       #pwm-cells = <3>;
> +                       status = "disabled";
> +               };
> +
>                 vin01: video@e6ef1000 {
>                         compatible = "renesas,vin-r8a779h0";
>                         reg = <0 0xe6ef1000 0 0x1000>;

However, TPU does not seem to work...

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH RFT 4/6] arm64: dts: renesas: r8a779h0: Add TPU device node

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 498 bytes --]

On Mon, Jul 29, 2024 at 08:44:33PM +0200, Geert Uytterhoeven wrote:
> On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
> <wsa+renesas@sang-engineering.com> wrote:
> > Add a device node for the 16-Bit Timer Pulse Unit (TPU) on the Renesas
> > R-Car V4H (R8A779G0) SoC.
> 
> R8A779H0

And V4M. Geez, where has my proof-reading gone :(

> > +               tpu: pwm@e6e80000 {
> 
> Move before spi@e6e90000...

OK. Do you want me to resend right away or wait for your further
testing?


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Re: [PATCH RFT 4/6] arm64: dts: renesas: r8a779h0: Add TPU device node

[Geert Uytterhoeven]

Hi Wolfram,

On Mon, Jul 29, 2024 at 9:01 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> On Mon, Jul 29, 2024 at 08:44:33PM +0200, Geert Uytterhoeven wrote:
> > On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
> > <wsa+renesas@sang-engineering.com> wrote:
> > > Add a device node for the 16-Bit Timer Pulse Unit (TPU) on the Renesas
> > > R-Car V4H (R8A779G0) SoC.
> >
> > R8A779H0
>
> And V4M. Geez, where has my proof-reading gone :(
>
> > > +               tpu: pwm@e6e80000 {
> >
> > Move before spi@e6e90000...
>
> OK. Do you want me to resend right away or wait for your further
> testing?

Given it doesn't work yet, I think there is no need to resend for now.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH RFT 5/6] arm64: dts: r8a779h0-gray-hawk-single: Add PWM support

[Wolfram Sang]

This patch enables PWM channels 1+2 on the GrayHawk board. Only for
testing, not for upstream.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 .../dts/renesas/r8a779h0-gray-hawk-single.dts | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
index 2b9a19bb1c5d..62878120673d 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
@@ -199,6 +199,16 @@ mmc_pins: mmc {
 		power-source = <1800>;
 	};
 
+	pwm1_pins: pwm1 {
+		groups = "pwm1_a";
+		function = "pwm1";
+	};
+
+	pwm2_pins: pwm2 {
+		groups = "pwm2_a";
+		function = "pwm2";
+	};
+
 	qspi0_pins: qspi0 {
 		groups = "qspi0_ctrl", "qspi0_data4";
 		function = "qspi0";
@@ -215,6 +225,20 @@ scif_clk2_pins: scif-clk2 {
 	};
 };
 
+&pwm1 {
+	pinctrl-0 = <&pwm1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-0 = <&pwm2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
 &rpc {
 	pinctrl-0 = <&qspi0_pins>;
 	pinctrl-names = "default";
-- 
2.43.0

Re: [PATCH RFT 5/6] arm64: dts: r8a779h0-gray-hawk-single: Add PWM support

[Geert Uytterhoeven]

Hi Wolfram,

On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> This patch enables PWM channels 1+2 on the GrayHawk board. Only for
> testing, not for upstream.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

I looked at PWM1 and PWM2 with an oscilloscope on test points CP174
and CP175, and played with them using sysfs. Period and duty cycle
look fine, so
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>

I had hoped to test PWM0, PWM3, and PWM4, too, as they are all available
on test points, but I couldn't locate CP238, CP240, and CP241.  The silk
screen for CP239 points underneath the heatsink, so probably all four
of them are obscured by the heatsink and/or switch board...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH RFT 6/6] arm64: dts: r8a779h0-gray-hawk-single: Add TPU support

[Wolfram Sang]

This patch enables TPU channel 1 for the GrayHawk board. Only for
testing, not for upstream.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 .../boot/dts/renesas/r8a779h0-gray-hawk-single.dts   | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
index 62878120673d..86d17950c017 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
@@ -223,6 +223,11 @@ scif_clk2_pins: scif-clk2 {
 		groups = "scif_clk2";
 		function = "scif_clk2";
 	};
+
+	tpu_pin: tpu {
+		groups = "tpu_to1";
+		function = "tpu";
+	};
 };
 
 &pwm1 {
@@ -279,3 +284,10 @@ &scif_clk {
 &scif_clk2 {
 	clock-frequency = <24000000>;
 };
+
+&tpu {
+	pinctrl-0 = <&tpu_pin>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
-- 
2.43.0

Re: [PATCH RFT 6/6] arm64: dts: r8a779h0-gray-hawk-single: Add TPU support

[Geert Uytterhoeven]

Hi Wolfram,

On Thu, Jul 25, 2024 at 9:49 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> This patch enables TPU channel 1 for the GrayHawk board. Only for
> testing, not for upstream.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
> @@ -223,6 +223,11 @@ scif_clk2_pins: scif-clk2 {
>                 groups = "scif_clk2";
>                 function = "scif_clk2";
>         };
> +
> +       tpu_pin: tpu {
> +               groups = "tpu_to1";

sh-pfc e6050000.pinctrl: invalid group "tpu_to1" for function "tpu"

This group does not exist. I assume you meant "tpu_to1_a"?

> +               function = "tpu";
> +       };
>  };
>
>  &pwm1 {
> @@ -279,3 +284,10 @@ &scif_clk {
>  &scif_clk2 {
>         clock-frequency = <24000000>;
>  };
> +
> +&tpu {
> +       pinctrl-0 = <&tpu_pin>;
> +       pinctrl-names = "default";
> +
> +       status = "okay";
> +};

Both tpu_to1(_a) and tpu_to2(_a) are available on CN3004, but I didn't
see any PWM signals on pins 10 and 12.  To be investigated further..

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH RFT 6/6] arm64: dts: r8a779h0-gray-hawk-single: Add TPU support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 588 bytes --]


> > +       tpu_pin: tpu {
> > +               groups = "tpu_to1";
> 
> sh-pfc e6050000.pinctrl: invalid group "tpu_to1" for function "tpu"
> 
> This group does not exist. I assume you meant "tpu_to1_a"?

Probably. I did test this via remote, though. Sorry, I assume this
hotfix got lost because the non-working pin got me distracted.

> Both tpu_to1(_a) and tpu_to2(_a) are available on CN3004, but I didn't
> see any PWM signals on pins 10 and 12.  To be investigated further..

I still assume they are driven low by something else. GPIO neither works
on these pins.


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Re: [PATCH RFT 6/6] arm64: dts: r8a779h0-gray-hawk-single: Add TPU support

[Geert Uytterhoeven]

Hi Wolfram,

On Mon, Jul 29, 2024 at 9:05 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> > > +       tpu_pin: tpu {
> > > +               groups = "tpu_to1";
> >
> > sh-pfc e6050000.pinctrl: invalid group "tpu_to1" for function "tpu"
> >
> > This group does not exist. I assume you meant "tpu_to1_a"?
>
> Probably. I did test this via remote, though. Sorry, I assume this
> hotfix got lost because the non-working pin got me distracted.
>
> > Both tpu_to1(_a) and tpu_to2(_a) are available on CN3004, but I didn't
> > see any PWM signals on pins 10 and 12.  To be investigated further..
>
> I still assume they are driven low by something else. GPIO neither works
> on these pins.

Indeed, I had tried using GP2_07 as remote-wake-up before, and that
also didn't work. The failing CANFD pins (still to be checked with
the scope) are also from bank 2, coincidence?

Keys (bank 5) and LEDs (bank 7) do work. I assume audio (bank0/1)
works, too.  I had briefly tried replacing i2c0 by i2c-gpio (bank 4),
and that also failed.

Perhaps there's a mistake in the register addresses for bank 2
(and bank 4?) in the PFC driver, or in the documentation?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH RFT 6/6] arm64: dts: r8a779h0-gray-hawk-single: Add TPU support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 247 bytes --]


> Perhaps there's a mistake in the register addresses for bank 2
> (and bank 4?) in the PFC driver, or in the documentation?

That would be way better than pins somehow wired to low and being
unusable on the board. I am keeping fingers crossed.


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Re: [PATCH RFT 0/6] PWM & TPU patches for V4M

[Rob Herring (Arm)]

On Thu, 25 Jul 2024 21:49:07 +0200, Wolfram Sang wrote:
> Here are the patches I prepared to enable PWM and TPU on the R-Car V4M
> SoC. Only patches 1-4 are for upstream, the rest are convenience patches
> for testers. They are based on linus-git as of today.
> 
> As discussed privately, Geert wants to have a try testing these. I
> cannot because testing needs physical access to HW which I don't have.
> Thanks, Geert!
> 
> 
> Cong Dang (2):
>   clk: renesas: r8a779h0: Add PWM clock
>   clk: renesas: r8a779h0: Add TPU clock
> 
> Khanh Le (1):
>   arm64: dts: renesas: r8a779h0: Add PWM device node
> 
> Wolfram Sang (3):
>   arm64: dts: renesas: r8a779h0: Add TPU device node
>   arm64: dts: r8a779h0-gray-hawk-single: Add PWM support
>   arm64: dts: r8a779h0-gray-hawk-single: Add TPU support
> 
>  .../dts/renesas/r8a779h0-gray-hawk-single.dts | 36 +++++++++++
>  arch/arm64/boot/dts/renesas/r8a779h0.dtsi     | 61 +++++++++++++++++++
>  drivers/clk/renesas/r8a779h0-cpg-mssr.c       |  2 +
>  3 files changed, 99 insertions(+)
> 
> --
> 2.43.0
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y renesas/r8a779h0-gray-hawk-single.dtb' for 20240725194906.14644-8-wsa+renesas@sang-engineering.com:

arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dtb: pwm@e6e30000: compatible:0: 'renesas,pwm-r8a779h0' is not one of ['renesas,pwm-r8a7742', 'renesas,pwm-r8a7743', 'renesas,pwm-r8a7744', 'renesas,pwm-r8a7745', 'renesas,pwm-r8a77470', 'renesas,pwm-r8a774a1', 'renesas,pwm-r8a774b1', 'renesas,pwm-r8a774c0', 'renesas,pwm-r8a774e1', 'renesas,pwm-r8a7778', 'renesas,pwm-r8a7779', 'renesas,pwm-r8a7790', 'renesas,pwm-r8a7791', 'renesas,pwm-r8a7794', 'renesas,pwm-r8a7795', 'renesas,pwm-r8a7796', 'renesas,pwm-r8a77961', 'renesas,pwm-r8a77965', 'renesas,pwm-r8a77970', 'renesas,pwm-r8a77980', 'renesas,pwm-r8a77990', 'renesas,pwm-r8a77995', 'renesas,pwm-r8a779a0', 'renesas,pwm-r8a779g0']
	from schema $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dtb: pwm@e6e31000: compatible:0: 'renesas,pwm-r8a779h0' is not one of ['renesas,pwm-r8a7742', 'renesas,pwm-r8a7743', 'renesas,pwm-r8a7744', 'renesas,pwm-r8a7745', 'renesas,pwm-r8a77470', 'renesas,pwm-r8a774a1', 'renesas,pwm-r8a774b1', 'renesas,pwm-r8a774c0', 'renesas,pwm-r8a774e1', 'renesas,pwm-r8a7778', 'renesas,pwm-r8a7779', 'renesas,pwm-r8a7790', 'renesas,pwm-r8a7791', 'renesas,pwm-r8a7794', 'renesas,pwm-r8a7795', 'renesas,pwm-r8a7796', 'renesas,pwm-r8a77961', 'renesas,pwm-r8a77965', 'renesas,pwm-r8a77970', 'renesas,pwm-r8a77980', 'renesas,pwm-r8a77990', 'renesas,pwm-r8a77995', 'renesas,pwm-r8a779a0', 'renesas,pwm-r8a779g0']
	from schema $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dtb: pwm@e6e32000: compatible:0: 'renesas,pwm-r8a779h0' is not one of ['renesas,pwm-r8a7742', 'renesas,pwm-r8a7743', 'renesas,pwm-r8a7744', 'renesas,pwm-r8a7745', 'renesas,pwm-r8a77470', 'renesas,pwm-r8a774a1', 'renesas,pwm-r8a774b1', 'renesas,pwm-r8a774c0', 'renesas,pwm-r8a774e1', 'renesas,pwm-r8a7778', 'renesas,pwm-r8a7779', 'renesas,pwm-r8a7790', 'renesas,pwm-r8a7791', 'renesas,pwm-r8a7794', 'renesas,pwm-r8a7795', 'renesas,pwm-r8a7796', 'renesas,pwm-r8a77961', 'renesas,pwm-r8a77965', 'renesas,pwm-r8a77970', 'renesas,pwm-r8a77980', 'renesas,pwm-r8a77990', 'renesas,pwm-r8a77995', 'renesas,pwm-r8a779a0', 'renesas,pwm-r8a779g0']
	from schema $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dtb: pwm@e6e33000: compatible:0: 'renesas,pwm-r8a779h0' is not one of ['renesas,pwm-r8a7742', 'renesas,pwm-r8a7743', 'renesas,pwm-r8a7744', 'renesas,pwm-r8a7745', 'renesas,pwm-r8a77470', 'renesas,pwm-r8a774a1', 'renesas,pwm-r8a774b1', 'renesas,pwm-r8a774c0', 'renesas,pwm-r8a774e1', 'renesas,pwm-r8a7778', 'renesas,pwm-r8a7779', 'renesas,pwm-r8a7790', 'renesas,pwm-r8a7791', 'renesas,pwm-r8a7794', 'renesas,pwm-r8a7795', 'renesas,pwm-r8a7796', 'renesas,pwm-r8a77961', 'renesas,pwm-r8a77965', 'renesas,pwm-r8a77970', 'renesas,pwm-r8a77980', 'renesas,pwm-r8a77990', 'renesas,pwm-r8a77995', 'renesas,pwm-r8a779a0', 'renesas,pwm-r8a779g0']
	from schema $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dtb: pwm@e6e34000: compatible:0: 'renesas,pwm-r8a779h0' is not one of ['renesas,pwm-r8a7742', 'renesas,pwm-r8a7743', 'renesas,pwm-r8a7744', 'renesas,pwm-r8a7745', 'renesas,pwm-r8a77470', 'renesas,pwm-r8a774a1', 'renesas,pwm-r8a774b1', 'renesas,pwm-r8a774c0', 'renesas,pwm-r8a774e1', 'renesas,pwm-r8a7778', 'renesas,pwm-r8a7779', 'renesas,pwm-r8a7790', 'renesas,pwm-r8a7791', 'renesas,pwm-r8a7794', 'renesas,pwm-r8a7795', 'renesas,pwm-r8a7796', 'renesas,pwm-r8a77961', 'renesas,pwm-r8a77965', 'renesas,pwm-r8a77970', 'renesas,pwm-r8a77980', 'renesas,pwm-r8a77990', 'renesas,pwm-r8a77995', 'renesas,pwm-r8a779a0', 'renesas,pwm-r8a779g0']
	from schema $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dtb: pwm@e6e80000: compatible:0: 'renesas,tpu-r8a779h0' is not one of ['renesas,tpu-r8a73a4', 'renesas,tpu-r8a7740', 'renesas,tpu-r8a7742', 'renesas,tpu-r8a7743', 'renesas,tpu-r8a7744', 'renesas,tpu-r8a7745', 'renesas,tpu-r8a7790', 'renesas,tpu-r8a7791', 'renesas,tpu-r8a7792', 'renesas,tpu-r8a7793', 'renesas,tpu-r8a7794', 'renesas,tpu-r8a7795', 'renesas,tpu-r8a7796', 'renesas,tpu-r8a77961', 'renesas,tpu-r8a77965', 'renesas,tpu-r8a77970', 'renesas,tpu-r8a77980', 'renesas,tpu-r8a779a0', 'renesas,tpu-r8a779g0']
	from schema $id: http://devicetree.org/schemas/pwm/renesas,tpu-pwm.yaml#