Re: [PATCH v3 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree

From: Sjoerd Simons <sjoerd@collabora.com>
To: Samuel Holland <samuel.holland@sifive.com>,
	Ariel D'Alessandro	 <ariel.dalessandro@collabora.com>,
	Pinkesh Vaghela	 <pinkesh.vaghela@einfochips.com>,
	Conor Dooley <conor@kernel.org>, Rob Herring	 <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Thomas Gleixner	 <tglx@linutronix.de>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt	 <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano	 <daniel.lezcano@linaro.org>,
	Min Lin <linmin@eswincomputing.com>,
	Pritesh Patel	 <pritesh.patel@einfochips.com>,
	Yangyu Chen <cyy@cyyself.name>,
	Lad Prabhakar	 <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Yu Chien Peter Lin	 <peterlin@andestech.com>,
	Charlie Jenkins <charlie@rivosinc.com>,
	Kanak Shilledar <kanakshilledar@gmail.com>,
	Darshan Prajapati <darshan.prajapati@einfochips.com>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Aradhya Bhatia	 <a-bhatia1@ti.com>,
	rafal@milecki.pl, Anup Patel <anup@brainfault.org>,
		devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
		linux-kernel@vger.kernel.org,
	"kernel@collabora.com" <kernel@collabora.com>
Subject: Re: [PATCH v3 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree
Date: Tue, 15 Apr 2025 09:39:21 +0200	[thread overview]
Message-ID: <096a8318629dea9073ad6c4807a2f1dedc6b0cd6.camel@collabora.com> (raw)
In-Reply-To: <0dc3bb03-3708-4134-96bf-d5f95187e8bb@sifive.com>

Hey,

On Mon, 2025-04-14 at 11:00 -0500, Samuel Holland wrote:
> Hi Ariel,
> 
> On 2025-04-14 7:55 AM, Ariel D'Alessandro wrote:
> > Hi Pinkesh,
> > 
> > On 4/10/25 12:25 PM, Pinkesh Vaghela wrote:
> > > From: Min Lin <linmin@eswincomputing.com>
> > 
<snip>

> > Although commit log says that this includes DRAM configuration, looks like
> > it's
> > missing? In order to test this patchset, had to add this following memory
> > definition (picked from vendor kernel repository):
> > 
> >     L50: memory@80000000 {
> >             compatible = "sifive,axi4-mem-port", "sifive,axi4-port",
> > "sifive,mem-port";
> >             device_type = "memory";
> >             reg = <0x0 0x80000000 0x7f 0x80000000>;
> >             sifive,port-width-bytes = <32>;
> >     };
> 
> That is a misstatement in the commit message. The memory node is not included
> in
> the static devicetree because the amount of RAM installed on the board is
> variable. It is the responsibility of firmware to provide the memory map,
> either
> through EFI or by patching the memory node into the DT at runtime. I believe
> the
> current BSP U-Boot does the former but not the latter.

Amount of RAM being variable is pretty common on devices using FDT these days;
Typically the dts still gets a memory node that's a reasonable default, with the
expectation that e.g. u-boot will fix it up. If you look at other risc-v
devicetrees in upstream they (almost?) all come with a pre-defined memory node.
For the P550 board a default memory node for 16G ram seems reasonable (as that
seems the minimal SKU?)

That all being said. Indeed the sifive BSP u-boot doesn't seem to call the
relevant `fdt_fixup_memory` to fixup the memory node, hence us having issues
booting with u-boot directly (without going through EFI). Honestly this was a
bit of a surprise to me as only most other architectures that's just done by
common code, but that doesn't seem to be the case for risc-v (either upstream or
downstream)

-- 
Sjoerd Simons
Collabora

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