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From: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
To: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Min Lin <linmin@eswincomputing.com>,
	Pritesh Patel <pritesh.patel@einfochips.com>,
	Yangyu Chen <cyy@cyyself.name>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Yu Chien Peter Lin <peterlin@andestech.com>,
	Charlie Jenkins <charlie@rivosinc.com>,
	Kanak Shilledar <kanakshilledar@gmail.com>,
	Darshan Prajapati <darshan.prajapati@einfochips.com>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Aradhya Bhatia <a-bhatia1@ti.com>,
	rafal@milecki.pl, Anup Patel <anup@brainfault.org>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree
Date: Mon, 14 Apr 2025 09:55:45 -0300	[thread overview]
Message-ID: <956d76b0-4f82-4f95-8f70-70896d488bd3@collabora.com> (raw)
In-Reply-To: <20250410152519.1358964-11-pinkesh.vaghela@einfochips.com>

Hi Pinkesh,

On 4/10/25 12:25 PM, Pinkesh Vaghela wrote:
> From: Min Lin <linmin@eswincomputing.com>
> 
> Add initial board data for HiFive Premier P550 Development board
> 
> Currently the data populated in this DT file describes the board
> DRAM configuration, UART and GPIO.
> 
> Signed-off-by: Min Lin <linmin@eswincomputing.com>
> Co-developed-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> Tested-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>   arch/riscv/boot/dts/Makefile                  |  1 +
>   arch/riscv/boot/dts/eswin/Makefile            |  2 ++
>   .../dts/eswin/eic7700-hifive-premier-p550.dts | 29 +++++++++++++++++++
>   3 files changed, 32 insertions(+)
>   create mode 100644 arch/riscv/boot/dts/eswin/Makefile
>   create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index 64a898da9aee..29a97a663ea2 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,6 +1,7 @@
>   # SPDX-License-Identifier: GPL-2.0
>   subdir-y += allwinner
>   subdir-y += canaan
> +subdir-y += eswin
>   subdir-y += microchip
>   subdir-y += renesas
>   subdir-y += sifive
> diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile
> new file mode 100644
> index 000000000000..224101ae471e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/eswin/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_ESWIN) += eic7700-hifive-premier-p550.dtb
> diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> new file mode 100644
> index 000000000000..131ed1fc6b2e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2024, Beijing ESWIN Computing Technology Co., Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include "eic7700.dtsi"
> +
> +/ {
> +	compatible = "sifive,hifive-premier-p550", "eswin,eic7700";
> +	model = "SiFive HiFive Premier P550";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	status = "okay";
> +};

Although commit log says that this includes DRAM configuration, looks 
like it's missing? In order to test this patchset, had to add this 
following memory definition (picked from vendor kernel repository):

     L50: memory@80000000 {
             compatible = "sifive,axi4-mem-port", "sifive,axi4-port", 
"sifive,mem-port";
             device_type = "memory";
             reg = <0x0 0x80000000 0x7f 0x80000000>;
             sifive,port-width-bytes = <32>;
     };

Regards,

-- 
Ariel D'Alessandro
Software Engineer

Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK 
Registered in England & Wales, no. 5513718


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  reply	other threads:[~2025-04-14 12:58 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-10 15:25 [PATCH v3 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 02/10] riscv: Add Kconfig option for ESWIN platforms Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 03/10] dt-bindings: vendor-prefixes: add eswin Pinkesh Vaghela
2025-04-10 17:33   ` Rob Herring (Arm)
2025-04-11  8:09     ` Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 04/10] dt-bindings: riscv: Add SiFive HiFive Premier P550 board Pinkesh Vaghela
2025-04-26 14:38   ` Jisheng Zhang
2025-05-23 10:04   ` 林敏
2025-04-10 15:25 ` [PATCH v3 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility Pinkesh Vaghela
2025-04-11 16:25   ` Conor Dooley
2025-04-10 15:25 ` [PATCH v3 06/10] cache: sifive_ccache: Add ESWIN EIC7700 support Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 07/10] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 08/10] dt-bindings: timer: Add ESWIN EIC7700 CLINT Pinkesh Vaghela
2025-05-14 15:18   ` Daniel Lezcano
2025-04-10 15:25 ` [PATCH v3 09/10] riscv: dts: add initial support for EIC7700 SoC Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree Pinkesh Vaghela
2025-04-14 12:55   ` Ariel D'Alessandro [this message]
2025-04-14 16:00     ` Samuel Holland
2025-04-15  7:39       ` Sjoerd Simons
2025-04-16 19:50         ` Ariel D'Alessandro
2025-04-26 14:32 ` [PATCH v3 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC Jisheng Zhang
2025-05-19 13:32   ` [External] " Pinkesh Vaghela

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