From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
To: Vincent Chen <vincent.chen@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH v3 1/2] RISC-V: Add support for restartable sequence
Date: Wed, 2 Mar 2022 11:29:23 -0500 (EST) [thread overview]
Message-ID: <1029793052.117276.1646238563508.JavaMail.zimbra@efficios.com> (raw)
In-Reply-To: <20220302023048.6140-2-vincent.chen@sifive.com>
----- On Mar 1, 2022, at 9:30 PM, Vincent Chen vincent.chen@sifive.com wrote:
> Add calls to rseq_signal_deliver() and rseq_syscall() to introduce RSEQ
> support.
>
> 1. Call the rseq_signal_deliver() function to fixup on the pre-signal
> frame when a signal is delivered on top of a restartable sequence
> critical section.
>
> 2. Check that system calls are not invoked from within rseq critical
> sections by invoking rseq_signal() from ret_from_syscall(). With
> CONFIG_DEBUG_RSEQ, such behavior results in termination of the
> process with SIGSEGV.
>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Will it be picked by by riscv maintainers ?
Thanks,
Mathieu
> ---
> arch/riscv/Kconfig | 1 +
> arch/riscv/kernel/entry.S | 4 ++++
> arch/riscv/kernel/signal.c | 2 ++
> 3 files changed, 7 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 5adcbd9b5e88..67a671b099b6 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -101,6 +101,7 @@ config RISCV
> select HAVE_FUNCTION_ARG_ACCESS_API
> select HAVE_STACKPROTECTOR
> select HAVE_SYSCALL_TRACEPOINTS
> + select HAVE_RSEQ
> select IRQ_DOMAIN
> select IRQ_FORCED_THREADING
> select MODULES_USE_ELF_RELA if MODULES
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index ed29e9c8f660..56ada2a583fa 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -225,6 +225,10 @@ ret_from_syscall:
> * (If it was configured with SECCOMP_RET_ERRNO/TRACE)
> */
> ret_from_syscall_rejected:
> +#ifdef CONFIG_DEBUG_RSEQ
> + move a0, sp
> + call rseq_syscall
> +#endif
> /* Trace syscalls, but only if requested by the user. */
> REG_L t0, TASK_TI_FLAGS(tp)
> andi t0, t0, _TIF_SYSCALL_WORK
> diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
> index c2d5ecbe5526..16da3c3b53a1 100644
> --- a/arch/riscv/kernel/signal.c
> +++ b/arch/riscv/kernel/signal.c
> @@ -258,6 +258,8 @@ static void handle_signal(struct ksignal *ksig, struct
> pt_regs *regs)
> }
> }
>
> + rseq_signal_deliver(ksig, regs);
> +
> /* Set up the stack frame */
> ret = setup_rt_frame(ksig, oldset, regs);
>
> --
> 2.17.1
--
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
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next prev parent reply other threads:[~2022-03-02 16:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-02 2:30 [PATCH v3 0/2] RISC-V: add support for restartable sequence Vincent Chen
2022-03-02 2:30 ` [PATCH v3 1/2] RISC-V: Add " Vincent Chen
2022-03-02 16:29 ` Mathieu Desnoyers [this message]
2022-03-03 3:32 ` Vincent Chen
2022-03-02 2:30 ` [PATCH v3 2/2] rseq/selftests: Add support for RISC-V Vincent Chen
2022-03-02 16:38 ` Mathieu Desnoyers
2022-03-03 7:16 ` Vincent Chen
2022-03-03 21:50 ` Mathieu Desnoyers
2022-03-04 6:50 ` Vincent Chen
2022-03-07 2:45 ` Vincent Chen
2022-03-07 13:40 ` Mathieu Desnoyers
2022-03-08 7:30 ` Eric Lin
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