[PATCH] Documentation: RISC-V: uabi: Only scalar misaligned loads are supported

[PATCH] Documentation: RISC-V: uabi: Only scalar misaligned loads are supported

[Palmer Dabbelt]

From: Palmer Dabbelt <palmer@rivosinc.com>

We're stuck supporting scalar misaligned loads in userspace because they
were part of the ISA at the time we froze the uABI.  That wasn't the
case for vector misaligned accesses, so depending on them
unconditionally is a userspace bug.  All extant vector hardware traps on
these misaligned accesses.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 Documentation/arch/riscv/uabi.rst | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/arch/riscv/uabi.rst b/Documentation/arch/riscv/uabi.rst
index 54d199dce78b..2b420bab0527 100644
--- a/Documentation/arch/riscv/uabi.rst
+++ b/Documentation/arch/riscv/uabi.rst
@@ -65,4 +65,6 @@ the extension, or may have deliberately removed it from the listing.
 Misaligned accesses
 -------------------
 
-Misaligned accesses are supported in userspace, but they may perform poorly.
+Misaligned scalar accesses are supported in userspace, but they may perform
+poorly.  Misaligned vector accesses are only supported if the Zicclsm extension
+is supported.
-- 
2.45.0


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Re: [PATCH] Documentation: RISC-V: uabi: Only scalar misaligned loads are supported

[Conor Dooley]

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On Fri, May 24, 2024 at 11:56:00AM -0700, Palmer Dabbelt wrote:
> From: Palmer Dabbelt <palmer@rivosinc.com>
> 
> We're stuck supporting scalar misaligned loads in userspace because they
> were part of the ISA at the time we froze the uABI.  That wasn't the
> case for vector misaligned accesses, so depending on them
> unconditionally is a userspace bug.  All extant vector hardware traps on
> these misaligned accesses.
> 
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
>  Documentation/arch/riscv/uabi.rst | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/arch/riscv/uabi.rst b/Documentation/arch/riscv/uabi.rst
> index 54d199dce78b..2b420bab0527 100644
> --- a/Documentation/arch/riscv/uabi.rst
> +++ b/Documentation/arch/riscv/uabi.rst
> @@ -65,4 +65,6 @@ the extension, or may have deliberately removed it from the listing.
>  Misaligned accesses
>  -------------------
>  
> -Misaligned accesses are supported in userspace, but they may perform poorly.
> +Misaligned scalar accesses are supported in userspace, but they may perform
> +poorly.  Misaligned vector accesses are only supported if the Zicclsm extension
> +is supported.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Now we just need to find someone that cares sufficiently about Zicclsm
to write the bindings, detection and hwprobe key for Zicclsm. Maybe I'll
be the lucky fool, depending on what the x280 does...

Thanks,
Conor.

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Re: [PATCH] Documentation: RISC-V: uabi: Only scalar misaligned loads are supported

[patchwork-bot+linux-riscv]

Hello:

This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Fri, 24 May 2024 11:56:00 -0700 you wrote:
> From: Palmer Dabbelt <palmer@rivosinc.com>
> 
> We're stuck supporting scalar misaligned loads in userspace because they
> were part of the ISA at the time we froze the uABI.  That wasn't the
> case for vector misaligned accesses, so depending on them
> unconditionally is a userspace bug.  All extant vector hardware traps on
> these misaligned accesses.
> 
> [...]

Here is the summary with links:
  - Documentation: RISC-V: uabi: Only scalar misaligned loads are supported
    https://git.kernel.org/riscv/c/982a7eb97be6

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
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