[PATCH] irqchip/sifive-plic: Avoid signed shift in interrupt enable mask

[PATCH] irqchip/sifive-plic: Avoid signed shift in interrupt enable mask

[Pengpeng Hou]

__plic_toggle() builds a 32-bit enable-register mask from the hardware
interrupt number. A valid interrupt whose low five bits are 31 evaluates
1 << 31, which shifts a signed int into its sign bit and is undefined
behavior.

Use BIT(), matching the equivalent mask construction in plic_irq_eoi().

Fixes: 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state")
Assisted-by: Codex:gpt-5
Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
---
 drivers/irqchip/irq-sifive-plic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 5b0dac104814..d3d4187b96ab 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -108,6 +108,6 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type);
 static void __plic_toggle(struct plic_handler *handler, int hwirq, int enable)
 {
 	u32 __iomem *base = handler->enable_base;
-	u32 hwirq_mask = 1 << (hwirq % 32);
+	u32 hwirq_mask = BIT(hwirq % 32);
 	int group = hwirq / 32;
 	u32 value;


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Re: [PATCH] irqchip/sifive-plic: Avoid signed shift in interrupt enable mask

[Radu Rendec]

On Tue, 2026-08-25 at 15:33 +0800, Pengpeng Hou wrote:
> __plic_toggle() builds a 32-bit enable-register mask from the hardware
> interrupt number. A valid interrupt whose low five bits are 31 evaluates
> 1 << 31, which shifts a signed int into its sign bit and is undefined
> behavior.
> 
> Use BIT(), matching the equivalent mask construction in plic_irq_eoi().
> 
> Fixes: 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state")

Thanks for the patch! The patch itself looks good but the Fixes tag
above does not correctly identify the commit that introduced the
problematic line. Ironically, that's one of the few lines in that
function that were *not* modified in that commit.

Please use "git blame" to find the right commit, and resend the patch
with a correct Fixes tag.

> Assisted-by: Codex:gpt-5
> Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
> ---
>  drivers/irqchip/irq-sifive-plic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index 5b0dac104814..d3d4187b96ab 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -108,6 +108,6 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type);
>  static void __plic_toggle(struct plic_handler *handler, int hwirq, int enable)
>  {
>  	u32 __iomem *base = handler->enable_base;
> -	u32 hwirq_mask = 1 << (hwirq % 32);
> +	u32 hwirq_mask = BIT(hwirq % 32);
>  	int group = hwirq / 32;
>  	u32 value;

-- 
Regards,
Radu

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