[RFC] Cache flush via SBI

[RFC] Cache flush via SBI

[Anup Patel]

Hi All,

I have gone through various discussions around cache flush/invalidate
operation not being part of RISC-V spec. Although, CPU designers can
still provide these operations in an implementation specific way.
Right?

My suggestion is to have SBI calls for cache flush/invalidate so that
platform specific firmware can
provide cache flush/invalidate in a more generic way. Thoughts??

I have one important use-case of why cache flush will be required for
virtualization (based on my previous experience in ARM
virtualization). The Guest/VM RAM will be mapped as normal (i.e.
cacheable memory) by QEMU+KVM but Guest OS will start with MMU
disabled. To ensure that Guest images loaded by QEMU are visible to
Guest at boot-time, the KVM kernel module will have to do cache flush.

Regards,
Anup

[RFC] Cache flush via SBI

[Christoph Hellwig]

On Mon, Jul 02, 2018 at 05:42:01PM +0530, Anup Patel wrote:
> Hi All,
> 
> I have gone through various discussions around cache flush/invalidate
> operation not being part of RISC-V spec. Although, CPU designers can
> still provide these operations in an implementation specific way.
> Right?
> 
> My suggestion is to have SBI calls for cache flush/invalidate so that
> platform specific firmware can
> provide cache flush/invalidate in a more generic way. Thoughts??

No, we need to add them to the spec.  In fact Jacob just sent out
anothet proposal to isa-dev, but I haven't had the time to go back
and review it yet.