From: Christoph Hellwig <hch@infradead.org>
To: Anup Patel <anup@brainfault.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <atish.patra@wdc.com>,
Anup Patel <anup.patel@wdc.com>, Gary Guo <gary@garyguo.net>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH 3/3] riscv: rewrite tlb flush for performance improvement
Date: Mon, 11 Mar 2019 08:53:14 -0700 [thread overview]
Message-ID: <20190311155314.GA21041@infradead.org> (raw)
In-Reply-To: <CAAhSdy18xNqbbQvBLj8pHB=vWM8KqhUfNN-6Bw7J4J2ONB8i=g@mail.gmail.com>
On Mon, Mar 11, 2019 at 02:19:54AM +0530, Anup Patel wrote:
> There are also use-cases to run two separate OSes on same SOC
> without virtualization. In such cases, both OSes cannot have access
> to CLINT for triggering IPIs.
And sometimes pigs can fly (no, really!). But we should optimize
for performance on hardware we have not build some ivory towers
for grand architectures of the future.
And with that I don't mean cutting corners and weird micro-optimization,
but to think hard what layering makes sense.
Having to trap into machine mode software to flush TLBs does not make
sense in any normal architecture.
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next prev parent reply other threads:[~2019-03-11 15:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-07 1:29 [PATCH 3/3] riscv: rewrite tlb flush for performance improvement Gary Guo
2019-03-08 14:39 ` Christoph Hellwig
2019-03-08 15:55 ` Gary Guo
2019-03-08 16:31 ` Christoph Hellwig
2019-03-08 16:50 ` Anup Patel
2019-03-08 17:18 ` Christoph Hellwig
2019-03-10 20:46 ` Anup Patel
2019-03-10 20:49 ` Anup Patel
2019-03-11 15:53 ` Christoph Hellwig [this message]
2019-03-11 16:28 ` Anup Patel
2019-03-08 16:46 ` Anup Patel
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