[v2] Add support for hwrng on PolarFire SoC

From: <conor.dooley@microchip.com>
To: <herbert@gondor.apana.org.au>
Cc: <linux-kernel@vger.kernel.org>, <linux-crypto@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: [v2] Add support for hwrng on PolarFire SoC
Date: Fri, 8 Apr 2022 10:09:11 +0000	[thread overview]
Message-ID: <20220408100911.1638478-1-conor.dooley@microchip.com> (raw)

From: Conor Dooley <conor.dooley@microchip.com>

As it says on the tin, add support for the hardware rng on PolarFire
SoC, which is accessed via the system controller.
I dropped the maintainers entry change that v1 had, I will send a
single update via RISCV to avoid any conflicts.

On v1 I replied saying there was a refcount issue, but that's not
actually the case, so no changes required there.

Thanks,
Conor

Changes since v1:
- Rebased on v5.18-rc1
- Dropped the MAINTAINERS change
- Added quality estimation

Conor Dooley (1):
  hwrng: mpfs - add polarfire soc hwrng support

 drivers/char/hw_random/Kconfig    |  13 ++++
 drivers/char/hw_random/Makefile   |   1 +
 drivers/char/hw_random/mpfs-rng.c | 104 ++++++++++++++++++++++++++++++
 3 files changed, 118 insertions(+)
 create mode 100644 drivers/char/hw_random/mpfs-rng.c

-- 
2.35.1

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv