From: Sergey Matyukevich <geomatsi@gmail.com>
To: linux-riscv@lists.infradead.org
Cc: Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>,
Sergey Matyukevich <geomatsi@gmail.com>,
Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Subject: [PATCH 1/3] perf: RISC-V: fix access beyond allocated array
Date: Thu, 23 Jun 2022 14:27:33 +0300 [thread overview]
Message-ID: <20220623112735.357093-2-geomatsi@gmail.com> (raw)
In-Reply-To: <20220623112735.357093-1-geomatsi@gmail.com>
From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Both OpenSBI and Linux driver explicitly assume that pmu counter IDs are
not expected to be contiguous. Namely, there is no hardware counter with
index 1: hardware uses that bit for TM control. However counter array is
allocated without that assumption. As a result, memory beyond allocated
array is accessed. Fix this by adding unused array element for index 1.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
---
drivers/perf/riscv_pmu_sbi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index dca3537a8dcc..3e0ea564b9b8 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -453,7 +453,7 @@ static int pmu_sbi_get_ctrinfo(int nctr)
int i, num_hw_ctr = 0, num_fw_ctr = 0;
union sbi_pmu_ctr_info cinfo;
- pmu_ctr_list = kcalloc(nctr, sizeof(*pmu_ctr_list), GFP_KERNEL);
+ pmu_ctr_list = kcalloc(nctr + 1, sizeof(*pmu_ctr_list), GFP_KERNEL);
if (!pmu_ctr_list)
return -ENOMEM;
--
2.36.1
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next prev parent reply other threads:[~2022-06-23 11:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-23 11:27 [PATCH 0/3] perf: RISC-V: fix access to the highest available counter Sergey Matyukevich
2022-06-23 11:27 ` Sergey Matyukevich [this message]
2022-06-23 17:50 ` [PATCH 1/3] perf: RISC-V: fix access beyond allocated array Atish Patra
2022-06-23 18:10 ` Sergey Matyukevich
2022-06-23 11:27 ` [PATCH 2/3] perf: RISC-V: allow to use the highest available counter Sergey Matyukevich
2022-06-23 17:59 ` Atish Patra
2022-06-23 11:27 ` [PATCH 3/3] perf: RISC-V: support noncontiguous pmu counter IDs Sergey Matyukevich
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