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From: Sergey Matyukevich <geomatsi@gmail.com>
To: linux-riscv@lists.infradead.org
Cc: Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	Sergey Matyukevich <geomatsi@gmail.com>,
	Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Subject: [PATCH 2/3] perf: RISC-V: allow to use the highest available counter
Date: Thu, 23 Jun 2022 14:27:34 +0300	[thread overview]
Message-ID: <20220623112735.357093-3-geomatsi@gmail.com> (raw)
In-Reply-To: <20220623112735.357093-1-geomatsi@gmail.com>

From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>

Both OpenSBI and Linux explicitly assume that there is no hardware counter
with index 1: hardware uses that bit for TM control. So OpenSBI filters
out that index in sanity checks. However its range sanity checks do not
treat that index in a special way. As a result, OpenSBI does not allow
to use the firmware counter with the highest index. Linux perf RISC-V
SBI driver is adapted for the current OpenSBI behavior: it excludes the
highest valid index from the counter mask passed to OpenSBI.

This patch fixes ranges to re-enable the highest available counter.

Accompanying OpenSBI fix to accept full mask:
- https://github.com/riscv-software-src/opensbi/pull/260

Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
---
 drivers/perf/riscv_pmu_sbi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 3e0ea564b9b8..294d4bded59e 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -265,7 +265,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event)
 	struct sbiret ret;
 	int idx;
 	uint64_t cbase = 0;
-	uint64_t cmask = GENMASK_ULL(rvpmu->num_counters - 1, 0);
+	uint64_t cmask = GENMASK_ULL(rvpmu->num_counters, 0);
 	unsigned long cflags = 0;
 
 	if (event->attr.exclude_kernel)
@@ -283,7 +283,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event)
 	}
 
 	idx = ret.value;
-	if (idx >= rvpmu->num_counters || !pmu_ctr_list[idx].value)
+	if (idx > rvpmu->num_counters || !pmu_ctr_list[idx].value)
 		return -ENOENT;
 
 	/* Additional sanity check for the counter id */
@@ -482,7 +482,7 @@ static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
 	 * which may include counters that are not enabled yet.
 	 */
 	sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
-		  0, GENMASK_ULL(pmu->num_counters - 1, 0), 0, 0, 0, 0);
+		  0, GENMASK_ULL(pmu->num_counters, 0), 0, 0, 0, 0);
 }
 
 static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu)
-- 
2.36.1


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  parent reply	other threads:[~2022-06-23 11:28 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-23 11:27 [PATCH 0/3] perf: RISC-V: fix access to the highest available counter Sergey Matyukevich
2022-06-23 11:27 ` [PATCH 1/3] perf: RISC-V: fix access beyond allocated array Sergey Matyukevich
2022-06-23 17:50   ` Atish Patra
2022-06-23 18:10     ` Sergey Matyukevich
2022-06-23 11:27 ` Sergey Matyukevich [this message]
2022-06-23 17:59   ` [PATCH 2/3] perf: RISC-V: allow to use the highest available counter Atish Patra
2022-06-23 11:27 ` [PATCH 3/3] perf: RISC-V: support noncontiguous pmu counter IDs Sergey Matyukevich

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