From: Conor Dooley <conor@kernel.org>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: linux-riscv@lists.infradead.org
Subject: Re: [PATCH 1/2] RISC-V: make ISA string workaround case-insensitive
Date: Sat, 22 Jul 2023 11:49:45 +0100 [thread overview]
Message-ID: <20230722-alongside-woven-ed0522ded939@spud> (raw)
In-Reply-To: <74ef735a676c3f21cbd8c2ee19d4a577a920f23e.1690006695.git.research_trasio@irq.a4lg.com>
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On Sat, Jul 22, 2023 at 06:22:37AM +0000, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> This is a follow-up for commit 255b34d799dd ("riscv: allow case-insensitive
> ISA string parsing").
>
> Although the QEMU workaround in the ISA string parser works well with
> lowercase-only handling ('s' followed by 'u' and not preceded by '_'),
> case-sensitive handling in the case-insensitive parser can be confusing.
> This commit makes the QEMU workaround case-insensitive and gives more
> robustness (against manually crafted Device Tree blobs) and less confusion
> to kernel developers.
If people are manually crafting their DT, they should check it for
compliance with dt-validate (or dtbs_check). The case insensitivity only
makes sense for ACPI, but by the time ACPI was supported, you'd already
removed the "su" stuff from QEMU.
Thanks,
Conor.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> ---
> arch/riscv/kernel/cpufeature.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index a8f66c015229..63277cdc1ea5 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -168,19 +168,19 @@ void __init riscv_fill_hwcap(void)
>
> switch (*ext) {
> case 's':
> + case 'S':
> /*
> * Workaround for invalid single-letter 's' & 'u'(QEMU).
> * No need to set the bit in riscv_isa as 's' & 'u' are
> * not valid ISA extensions. It works until multi-letter
> * extension starting with "Su" appears.
> */
> - if (ext[-1] != '_' && ext[1] == 'u') {
> + if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
> ++isa;
> ext_err = true;
> break;
> }
> fallthrough;
> - case 'S':
> case 'x':
> case 'X':
> case 'z':
> --
> 2.40.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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next prev parent reply other threads:[~2023-07-22 10:50 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-22 6:22 [PATCH 0/2] RISC-V: minor fixes to the QEMU workaround in ISA string parser Tsukasa OI
2023-07-22 6:22 ` [PATCH 1/2] RISC-V: make ISA string workaround case-insensitive Tsukasa OI
2023-07-22 10:49 ` Conor Dooley [this message]
2023-07-22 6:22 ` [PATCH 2/2] RISC-V: fix the comment for ISA string workaround Tsukasa OI
2023-07-22 10:52 ` Conor Dooley
2023-07-22 11:22 ` Tsukasa OI
2023-07-22 11:28 ` Conor Dooley
2023-07-26 5:44 ` [PATCH v2 0/1] RISC-V: clarification of the QEMU workaround in the ISA parser Tsukasa OI
2023-07-26 5:44 ` [PATCH v2 1/1] RISC-V: clarify the QEMU workaround in " Tsukasa OI
2023-07-26 6:56 ` Conor Dooley
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