Re: [PATCH v2 1/1] RISC-V: clarify the QEMU workaround in ISA parser

[Conor Dooley <conor.dooley@microchip.com>]

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On Wed, Jul 26, 2023 at 05:44:16AM +0000, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> Extensions prefixed with "Su" won't corrupt the workaround in many
> cases.  The only exception is when the first multi-letter extension in the
> ISA string begins with "Su" and is not prefixed with an underscore.
> 
> For instance, following ISA string can confuse this QEMU workaround.
> 
> *   "rv64imacsuclic" (RV64I + M + A + C + "Suclic")
> 
> However, this case is very unlikely because extensions prefixed by either
> "Z", "Sm" or "Ss" will most likely precede first.
> 
> For instance, the "Suclic" extension (draft as of now) will be placed after
> related "Smclic" and "Ssclic" extensions.  It's also highly likely that
> other unprivileged extensions like "Zba" will precede.
> 
> It's also possible to suppress the issue in the QEMU workaround with an
> underscore.  Following ISA string won't confuse the QEMU workaround.
> 
> *   "rv64imac_suclic" (RV64I + M + A + C + delimited "Suclic")
> 
> This fix is to tell kernel developers the nature of this workaround
> precisely.  There are some "Su*" extensions to be ratified but don't worry
> about this workaround too much.
> 
> This commit comes with other minor editorial fixes (for minor wording and
> spacing issues, without changing the meaning).
> 
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>

Pretty sure I gave you a Reviewed-by last time? Nevertheless,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

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