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* [PATCH] riscv: dts: starfive: fix jh7110 qspi sort order
@ 2023-08-15 10:38 Conor Dooley
  2023-08-15 10:42 ` Emil Renner Berthing
  0 siblings, 1 reply; 3+ messages in thread
From: Conor Dooley @ 2023-08-15 10:38 UTC (permalink / raw)
  To: linux-riscv; +Cc: conor, Conor Dooley, Emil Renner Berthing

From: Conor Dooley <conor.dooley@microchip.com>

Emil pointed out that "13010000 sorts after 12070000". Reshuffle the
entries to be in-order.

Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 38 ++++++++++++------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 9aa563898868..e85464c328d0 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -676,25 +676,6 @@ i2c6: i2c@12060000 {
 			status = "disabled";
 		};
 
-		qspi: spi@13010000 {
-			compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
-			reg = <0x0 0x13010000 0x0 0x10000>,
-			      <0x0 0x21000000 0x0 0x400000>;
-			interrupts = <25>;
-			clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
-				 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
-				 <&syscrg JH7110_SYSCLK_QSPI_APB>;
-			clock-names = "ref", "ahb", "apb";
-			resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
-				 <&syscrg JH7110_SYSRST_QSPI_AHB>,
-				 <&syscrg JH7110_SYSRST_QSPI_REF>;
-			reset-names = "qspi", "qspi-ocp", "rstc_ref";
-			cdns,fifo-depth = <256>;
-			cdns,fifo-width = <4>;
-			cdns,trigger-address = <0x0>;
-			status = "disabled";
-		};
-
 		spi3: spi@12070000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x0 0x12070000 0x0 0x10000>;
@@ -767,6 +748,25 @@ sfctemp: temperature-sensor@120e0000 {
 			#thermal-sensor-cells = <0>;
 		};
 
+		qspi: spi@13010000 {
+			compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+			reg = <0x0 0x13010000 0x0 0x10000>,
+			      <0x0 0x21000000 0x0 0x400000>;
+			interrupts = <25>;
+			clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
+				 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
+				 <&syscrg JH7110_SYSCLK_QSPI_APB>;
+			clock-names = "ref", "ahb", "apb";
+			resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+				 <&syscrg JH7110_SYSRST_QSPI_AHB>,
+				 <&syscrg JH7110_SYSRST_QSPI_REF>;
+			reset-names = "qspi", "qspi-ocp", "rstc_ref";
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x0>;
+			status = "disabled";
+		};
+
 		syscrg: clock-controller@13020000 {
 			compatible = "starfive,jh7110-syscrg";
 			reg = <0x0 0x13020000 0x0 0x10000>;
-- 
2.39.2


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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: dts: starfive: fix jh7110 qspi sort order
  2023-08-15 10:38 [PATCH] riscv: dts: starfive: fix jh7110 qspi sort order Conor Dooley
@ 2023-08-15 10:42 ` Emil Renner Berthing
  2023-08-15 13:24   ` Conor Dooley
  0 siblings, 1 reply; 3+ messages in thread
From: Emil Renner Berthing @ 2023-08-15 10:42 UTC (permalink / raw)
  To: Conor Dooley; +Cc: linux-riscv, Conor Dooley

On Tue, 15 Aug 2023 at 12:38, Conor Dooley <conor@kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Emil pointed out that "13010000 sorts after 12070000". Reshuffle the
> entries to be in-order.
>
> Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>

Thanks!
Reviewed-by: Emil Renner Berthing <emil.renner.berthign@canonical.com>

> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 38 ++++++++++++------------
>  1 file changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 9aa563898868..e85464c328d0 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -676,25 +676,6 @@ i2c6: i2c@12060000 {
>                         status = "disabled";
>                 };
>
> -               qspi: spi@13010000 {
> -                       compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
> -                       reg = <0x0 0x13010000 0x0 0x10000>,
> -                             <0x0 0x21000000 0x0 0x400000>;
> -                       interrupts = <25>;
> -                       clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
> -                                <&syscrg JH7110_SYSCLK_QSPI_AHB>,
> -                                <&syscrg JH7110_SYSCLK_QSPI_APB>;
> -                       clock-names = "ref", "ahb", "apb";
> -                       resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
> -                                <&syscrg JH7110_SYSRST_QSPI_AHB>,
> -                                <&syscrg JH7110_SYSRST_QSPI_REF>;
> -                       reset-names = "qspi", "qspi-ocp", "rstc_ref";
> -                       cdns,fifo-depth = <256>;
> -                       cdns,fifo-width = <4>;
> -                       cdns,trigger-address = <0x0>;
> -                       status = "disabled";
> -               };
> -
>                 spi3: spi@12070000 {
>                         compatible = "arm,pl022", "arm,primecell";
>                         reg = <0x0 0x12070000 0x0 0x10000>;
> @@ -767,6 +748,25 @@ sfctemp: temperature-sensor@120e0000 {
>                         #thermal-sensor-cells = <0>;
>                 };
>
> +               qspi: spi@13010000 {
> +                       compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
> +                       reg = <0x0 0x13010000 0x0 0x10000>,
> +                             <0x0 0x21000000 0x0 0x400000>;
> +                       interrupts = <25>;
> +                       clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
> +                                <&syscrg JH7110_SYSCLK_QSPI_AHB>,
> +                                <&syscrg JH7110_SYSCLK_QSPI_APB>;
> +                       clock-names = "ref", "ahb", "apb";
> +                       resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
> +                                <&syscrg JH7110_SYSRST_QSPI_AHB>,
> +                                <&syscrg JH7110_SYSRST_QSPI_REF>;
> +                       reset-names = "qspi", "qspi-ocp", "rstc_ref";
> +                       cdns,fifo-depth = <256>;
> +                       cdns,fifo-width = <4>;
> +                       cdns,trigger-address = <0x0>;
> +                       status = "disabled";
> +               };
> +
>                 syscrg: clock-controller@13020000 {
>                         compatible = "starfive,jh7110-syscrg";
>                         reg = <0x0 0x13020000 0x0 0x10000>;
> --
> 2.39.2
>

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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: dts: starfive: fix jh7110 qspi sort order
  2023-08-15 10:42 ` Emil Renner Berthing
@ 2023-08-15 13:24   ` Conor Dooley
  0 siblings, 0 replies; 3+ messages in thread
From: Conor Dooley @ 2023-08-15 13:24 UTC (permalink / raw)
  To: Emil Renner Berthing; +Cc: linux-riscv, Conor Dooley


[-- Attachment #1.1: Type: text/plain, Size: 615 bytes --]

On Tue, Aug 15, 2023 at 12:42:25PM +0200, Emil Renner Berthing wrote:
> On Tue, 15 Aug 2023 at 12:38, Conor Dooley <conor@kernel.org> wrote:
> >
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > Emil pointed out that "13010000 sorts after 12070000". Reshuffle the
> > entries to be in-order.
> >
> > Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> 
> Thanks!
> Reviewed-by: Emil Renner Berthing <emil.renner.berthign@canonical.com>

Should be pushed. I'll send it this window if I am supposed to take the
Beagle Ahead bits, otherwise at some point in the future...

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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 3+ messages in thread
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2023-08-15 10:38 [PATCH] riscv: dts: starfive: fix jh7110 qspi sort order Conor Dooley
2023-08-15 10:42 ` Emil Renner Berthing
2023-08-15 13:24   ` Conor Dooley

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