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* [PATCH] riscv: dts: sophgo: remove address-cells from CV1800B intc node
@ 2023-11-13  9:26 Inochi Amaoto
  2023-11-13 13:14 ` Conor Dooley
  0 siblings, 1 reply; 3+ messages in thread
From: Inochi Amaoto @ 2023-11-13  9:26 UTC (permalink / raw)
  To: Chao Wei, Chen Wang, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Jisheng Zhang
  Cc: Inochi Amaoto, devicetree, linux-riscv, linux-kernel

A recent submission from Rob has added additionalProperties: false
to the interrupt-controller child node of RISC-V cpus. But CV1800B does
not follow this change and still uses #address-cells in its interrupt
controller. As it has no child nodes, #address-cells is not needed and
can be removed.

Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index df40e87ee063..aec6401a467b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -34,7 +34,6 @@ cpu0: cpu@0 {
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
-				#address-cells = <0>;
 				#interrupt-cells = <1>;
 			};
 		};
--
2.42.1


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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: remove address-cells from CV1800B intc node
  2023-11-13  9:26 [PATCH] riscv: dts: sophgo: remove address-cells from CV1800B intc node Inochi Amaoto
@ 2023-11-13 13:14 ` Conor Dooley
  2023-11-14  0:41   ` Inochi Amaoto
  0 siblings, 1 reply; 3+ messages in thread
From: Conor Dooley @ 2023-11-13 13:14 UTC (permalink / raw)
  To: Inochi Amaoto
  Cc: Chao Wei, Chen Wang, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Jisheng Zhang, devicetree, linux-riscv, linux-kernel


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On Mon, Nov 13, 2023 at 05:26:15PM +0800, Inochi Amaoto wrote:
> A recent submission from Rob has added additionalProperties: false
> to the interrupt-controller child node of RISC-V cpus. But CV1800B does
> not follow this change and still uses #address-cells in its interrupt
> controller. As it has no child nodes, #address-cells is not needed and
> can be removed.
> 
> Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
> Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/

This is a dupe of a patch I already applied, but have not yet sent a PR
for:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/commit/?h=riscv-dt-for-next&id=b99df62818919b84e970eea5aec60b0dbc57da18

Cheers,
Conor.

> 
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index df40e87ee063..aec6401a467b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -34,7 +34,6 @@ cpu0: cpu@0 {
>  			cpu0_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
>  				interrupt-controller;
> -				#address-cells = <0>;
>  				#interrupt-cells = <1>;
>  			};
>  		};
> --
> 2.42.1
> 

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^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: dts: sophgo: remove address-cells from CV1800B intc node
  2023-11-13 13:14 ` Conor Dooley
@ 2023-11-14  0:41   ` Inochi Amaoto
  0 siblings, 0 replies; 3+ messages in thread
From: Inochi Amaoto @ 2023-11-14  0:41 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Inochi Amaoto, Chao Wei, Chen Wang, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
	Albert Ou, Jisheng Zhang, devicetree, linux-riscv, linux-kernel

>On Mon, Nov 13, 2023 at 05:26:15PM +0800, Inochi Amaoto wrote:
>> A recent submission from Rob has added additionalProperties: false
>> to the interrupt-controller child node of RISC-V cpus. But CV1800B does
>> not follow this change and still uses #address-cells in its interrupt
>> controller. As it has no child nodes, #address-cells is not needed and
>> can be removed.
>>
>> Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
>> Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/
>
>This is a dupe of a patch I already applied, but have not yet sent a PR

OK, I will try to check the tree next time.

>for:
>https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/commit/?h=riscv-dt-for-next&id=b99df62818919b84e970eea5aec60b0dbc57da18
>

Thanks.

>Cheers,
>Conor.
>
>>
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>> ---
>>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
>>  1 file changed, 1 deletion(-)
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> index df40e87ee063..aec6401a467b 100644
>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> @@ -34,7 +34,6 @@ cpu0: cpu@0 {
>>  			cpu0_intc: interrupt-controller {
>>  				compatible = "riscv,cpu-intc";
>>  				interrupt-controller;
>> -				#address-cells = <0>;
>>  				#interrupt-cells = <1>;
>>  			};
>>  		};
>> --
>> 2.42.1
>>
>

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^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-11-14  0:41 UTC | newest]

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2023-11-13  9:26 [PATCH] riscv: dts: sophgo: remove address-cells from CV1800B intc node Inochi Amaoto
2023-11-13 13:14 ` Conor Dooley
2023-11-14  0:41   ` Inochi Amaoto

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