* [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and two-byte cmpxchg [not found] <31c82dcc-e203-48a9-aadd-f2fcd57d94c1@paulmck-laptop> @ 2024-04-01 21:39 ` Paul E. McKenney 2024-04-04 14:15 ` Palmer Dabbelt 0 siblings, 1 reply; 6+ messages in thread From: Paul E. McKenney @ 2024-04-01 21:39 UTC (permalink / raw) To: linux-kernel Cc: kernel-team, Paul E. McKenney, Andi Shyti, Andrzej Hajda, linux-riscv Use the new cmpxchg_emu_u8() and cmpxchg_emu_u16() to emulate one-byte and two-byte cmpxchg() on riscv. [ paulmck: Apply kernel test robot feedback. ] Signed-off-by: Paul E. McKenney <paulmck@kernel.org> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Andrzej Hajda <andrzej.hajda@intel.com> Cc: <linux-riscv@lists.infradead.org> --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/cmpxchg.h | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index be09c8836d56b..4eaf40d0a52ec 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -44,6 +44,7 @@ config RISCV select ARCH_HAS_UBSAN select ARCH_HAS_VDSO_DATA select ARCH_KEEP_MEMBLOCK if ACPI + select ARCH_NEED_CMPXCHG_1_2_EMU select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT select ARCH_STACKWALK diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 2fee65cc84432..a5b377481785c 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -9,6 +9,7 @@ #include <linux/bug.h> #include <asm/fence.h> +#include <linux/cmpxchg-emu.h> #define __xchg_relaxed(ptr, new, size) \ ({ \ @@ -170,6 +171,12 @@ __typeof__(*(ptr)) __ret; \ register unsigned int __rc; \ switch (size) { \ + case 1: \ + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ + break; \ + case 2: \ + break; \ + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ case 4: \ __asm__ __volatile__ ( \ "0: lr.w %0, %2\n" \ @@ -214,6 +221,12 @@ __typeof__(*(ptr)) __ret; \ register unsigned int __rc; \ switch (size) { \ + case 1: \ + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ + break; \ + case 2: \ + break; \ + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ case 4: \ __asm__ __volatile__ ( \ "0: lr.w %0, %2\n" \ @@ -260,6 +273,12 @@ __typeof__(*(ptr)) __ret; \ register unsigned int __rc; \ switch (size) { \ + case 1: \ + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ + break; \ + case 2: \ + break; \ + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ case 4: \ __asm__ __volatile__ ( \ RISCV_RELEASE_BARRIER \ @@ -306,6 +325,12 @@ __typeof__(*(ptr)) __ret; \ register unsigned int __rc; \ switch (size) { \ + case 1: \ + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ + break; \ + case 2: \ + break; \ + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ case 4: \ __asm__ __volatile__ ( \ "0: lr.w %0, %2\n" \ -- 2.40.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and two-byte cmpxchg 2024-04-01 21:39 ` [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and two-byte cmpxchg Paul E. McKenney @ 2024-04-04 14:15 ` Palmer Dabbelt 2024-04-04 14:50 ` Paul E. McKenney 2024-05-11 6:50 ` Guo Ren 0 siblings, 2 replies; 6+ messages in thread From: Palmer Dabbelt @ 2024-04-04 14:15 UTC (permalink / raw) To: paulmck Cc: linux-kernel, kernel-team, paulmck, andi.shyti, andrzej.hajda, linux-riscv On Mon, 01 Apr 2024 14:39:50 PDT (-0700), paulmck@kernel.org wrote: > Use the new cmpxchg_emu_u8() and cmpxchg_emu_u16() to emulate one-byte > and two-byte cmpxchg() on riscv. > > [ paulmck: Apply kernel test robot feedback. ] I'm not entirely following the thread, but sounds like there's going to be generic kernel users of this now? Before we'd said "no" to the byte/half atomic emulation routines beacuse they weren't used, but if it's a generic thing then I'm find adding them. There's a patch set over here <https://lore.kernel.org/all/20240103163203.72768-2-leobras@redhat.com/> that implements these more directly using LR/SC. I was sort of on the fence about just taking it even with no direct users right now, as the byte/half atomic extension is working its way through the spec process so we'll have them for real soon. I stopped right there for the last merge window, though, as I figured it was too late to be messing with the atomics... So Acked-by: Palmer Dabbelt <palmer@rivosinc.com> if you guys want to take some sort of tree-wide change to make the byte/half stuff be required everywhere. We'll eventually end up with arch routines for the extension, so at that point we might as well also have the more direct LR/SC flavors. If you want I can go review/merge that RISC-V patch set and then it'll have time to bake for a shared tag you can pick up for all this stuff? No rush on my end, just LMK. > Signed-off-by: Paul E. McKenney <paulmck@kernel.org> > Cc: Andi Shyti <andi.shyti@linux.intel.com> > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > Cc: <linux-riscv@lists.infradead.org> > --- > arch/riscv/Kconfig | 1 + > arch/riscv/include/asm/cmpxchg.h | 25 +++++++++++++++++++++++++ > 2 files changed, 26 insertions(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index be09c8836d56b..4eaf40d0a52ec 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -44,6 +44,7 @@ config RISCV > select ARCH_HAS_UBSAN > select ARCH_HAS_VDSO_DATA > select ARCH_KEEP_MEMBLOCK if ACPI > + select ARCH_NEED_CMPXCHG_1_2_EMU > select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX > select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT > select ARCH_STACKWALK > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > index 2fee65cc84432..a5b377481785c 100644 > --- a/arch/riscv/include/asm/cmpxchg.h > +++ b/arch/riscv/include/asm/cmpxchg.h > @@ -9,6 +9,7 @@ > #include <linux/bug.h> > > #include <asm/fence.h> > +#include <linux/cmpxchg-emu.h> > > #define __xchg_relaxed(ptr, new, size) \ > ({ \ > @@ -170,6 +171,12 @@ > __typeof__(*(ptr)) __ret; \ > register unsigned int __rc; \ > switch (size) { \ > + case 1: \ > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > + break; \ > + case 2: \ > + break; \ > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > case 4: \ > __asm__ __volatile__ ( \ > "0: lr.w %0, %2\n" \ > @@ -214,6 +221,12 @@ > __typeof__(*(ptr)) __ret; \ > register unsigned int __rc; \ > switch (size) { \ > + case 1: \ > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > + break; \ > + case 2: \ > + break; \ > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > case 4: \ > __asm__ __volatile__ ( \ > "0: lr.w %0, %2\n" \ > @@ -260,6 +273,12 @@ > __typeof__(*(ptr)) __ret; \ > register unsigned int __rc; \ > switch (size) { \ > + case 1: \ > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > + break; \ > + case 2: \ > + break; \ > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > case 4: \ > __asm__ __volatile__ ( \ > RISCV_RELEASE_BARRIER \ > @@ -306,6 +325,12 @@ > __typeof__(*(ptr)) __ret; \ > register unsigned int __rc; \ > switch (size) { \ > + case 1: \ > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > + break; \ > + case 2: \ > + break; \ > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > case 4: \ > __asm__ __volatile__ ( \ > "0: lr.w %0, %2\n" \ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and two-byte cmpxchg 2024-04-04 14:15 ` Palmer Dabbelt @ 2024-04-04 14:50 ` Paul E. McKenney 2024-05-11 6:50 ` Guo Ren 1 sibling, 0 replies; 6+ messages in thread From: Paul E. McKenney @ 2024-04-04 14:50 UTC (permalink / raw) To: Palmer Dabbelt Cc: linux-kernel, kernel-team, andi.shyti, andrzej.hajda, linux-riscv On Thu, Apr 04, 2024 at 07:15:40AM -0700, Palmer Dabbelt wrote: > On Mon, 01 Apr 2024 14:39:50 PDT (-0700), paulmck@kernel.org wrote: > > Use the new cmpxchg_emu_u8() and cmpxchg_emu_u16() to emulate one-byte > > and two-byte cmpxchg() on riscv. > > > > [ paulmck: Apply kernel test robot feedback. ] > > I'm not entirely following the thread, but sounds like there's going to be > generic kernel users of this now? Before we'd said "no" to the byte/half > atomic emulation routines beacuse they weren't used, but if it's a generic > thing then I'm find adding them. RCU currently contains an open-coded counterpart of the proposed cmpxchg_emu_u8() function, so yes. ;-) > There's a patch set over here > <https://lore.kernel.org/all/20240103163203.72768-2-leobras@redhat.com/> > that implements these more directly using LR/SC. I was sort of on the fence > about just taking it even with no direct users right now, as the byte/half > atomic extension is working its way through the spec process so we'll have > them for real soon. I stopped right there for the last merge window, > though, as I figured it was too late to be messing with the atomics... I would be extremely happy to drop my riscv patch in favor of an architecture-specific implementation, especially a more-efficient implementation. ;-) > So > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > if you guys want to take some sort of tree-wide change to make the byte/half > stuff be required everywhere. We'll eventually end up with arch routines > for the extension, so at that point we might as well also have the more > direct LR/SC flavors. > > If you want I can go review/merge that RISC-V patch set and then it'll have > time to bake for a shared tag you can pick up for all this stuff? No rush > on my end, just LMK. That sounds very good! I will apply your ack to my emulatino commit in the meantime, so your schedule is my schedule. And a big "thank you!" for both!!! Thanx, Paul > > Signed-off-by: Paul E. McKenney <paulmck@kernel.org> > > Cc: Andi Shyti <andi.shyti@linux.intel.com> > > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > > Cc: <linux-riscv@lists.infradead.org> > > --- > > arch/riscv/Kconfig | 1 + > > arch/riscv/include/asm/cmpxchg.h | 25 +++++++++++++++++++++++++ > > 2 files changed, 26 insertions(+) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index be09c8836d56b..4eaf40d0a52ec 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -44,6 +44,7 @@ config RISCV > > select ARCH_HAS_UBSAN > > select ARCH_HAS_VDSO_DATA > > select ARCH_KEEP_MEMBLOCK if ACPI > > + select ARCH_NEED_CMPXCHG_1_2_EMU > > select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX > > select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT > > select ARCH_STACKWALK > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > > index 2fee65cc84432..a5b377481785c 100644 > > --- a/arch/riscv/include/asm/cmpxchg.h > > +++ b/arch/riscv/include/asm/cmpxchg.h > > @@ -9,6 +9,7 @@ > > #include <linux/bug.h> > > > > #include <asm/fence.h> > > +#include <linux/cmpxchg-emu.h> > > > > #define __xchg_relaxed(ptr, new, size) \ > > ({ \ > > @@ -170,6 +171,12 @@ > > __typeof__(*(ptr)) __ret; \ > > register unsigned int __rc; \ > > switch (size) { \ > > + case 1: \ > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > + break; \ > > + case 2: \ > > + break; \ > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > case 4: \ > > __asm__ __volatile__ ( \ > > "0: lr.w %0, %2\n" \ > > @@ -214,6 +221,12 @@ > > __typeof__(*(ptr)) __ret; \ > > register unsigned int __rc; \ > > switch (size) { \ > > + case 1: \ > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > + break; \ > > + case 2: \ > > + break; \ > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > case 4: \ > > __asm__ __volatile__ ( \ > > "0: lr.w %0, %2\n" \ > > @@ -260,6 +273,12 @@ > > __typeof__(*(ptr)) __ret; \ > > register unsigned int __rc; \ > > switch (size) { \ > > + case 1: \ > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > + break; \ > > + case 2: \ > > + break; \ > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > case 4: \ > > __asm__ __volatile__ ( \ > > RISCV_RELEASE_BARRIER \ > > @@ -306,6 +325,12 @@ > > __typeof__(*(ptr)) __ret; \ > > register unsigned int __rc; \ > > switch (size) { \ > > + case 1: \ > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > + break; \ > > + case 2: \ > > + break; \ > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > case 4: \ > > __asm__ __volatile__ ( \ > > "0: lr.w %0, %2\n" \ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and two-byte cmpxchg 2024-04-04 14:15 ` Palmer Dabbelt 2024-04-04 14:50 ` Paul E. McKenney @ 2024-05-11 6:50 ` Guo Ren 2024-05-11 14:54 ` Paul E. McKenney 1 sibling, 1 reply; 6+ messages in thread From: Guo Ren @ 2024-05-11 6:50 UTC (permalink / raw) To: Leonardo Bras Cc: paulmck, linux-kernel, kernel-team, andi.shyti, andrzej.hajda, linux-riscv, palmer On Thu, Apr 04, 2024 at 07:15:40AM -0700, Palmer Dabbelt wrote: > On Mon, 01 Apr 2024 14:39:50 PDT (-0700), paulmck@kernel.org wrote: > > Use the new cmpxchg_emu_u8() and cmpxchg_emu_u16() to emulate one-byte > > and two-byte cmpxchg() on riscv. > > > > [ paulmck: Apply kernel test robot feedback. ] > > I'm not entirely following the thread, but sounds like there's going to be > generic kernel users of this now? Before we'd said "no" to the byte/half > atomic emulation routines beacuse they weren't used, but if it's a generic > thing then I'm find adding them. > > There's a patch set over here > <https://lore.kernel.org/all/20240103163203.72768-2-leobras@redhat.com/> > that implements these more directly using LR/SC. I was sort of on the fence > about just taking it even with no direct users right now, as the byte/half > atomic extension is working its way through the spec process so we'll have > them for real soon. I stopped right there for the last merge window, > though, as I figured it was too late to be messing with the atomics... > > So > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> F.Y.I Leonardo Bras <leobras@redhat.com> > > if you guys want to take some sort of tree-wide change to make the byte/half > stuff be required everywhere. We'll eventually end up with arch routines > for the extension, so at that point we might as well also have the more > direct LR/SC flavors. > > If you want I can go review/merge that RISC-V patch set and then it'll have > time to bake for a shared tag you can pick up for all this stuff? No rush > on my end, just LMK. > > > Signed-off-by: Paul E. McKenney <paulmck@kernel.org> > > Cc: Andi Shyti <andi.shyti@linux.intel.com> > > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > > Cc: <linux-riscv@lists.infradead.org> > > --- > > arch/riscv/Kconfig | 1 + > > arch/riscv/include/asm/cmpxchg.h | 25 +++++++++++++++++++++++++ > > 2 files changed, 26 insertions(+) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index be09c8836d56b..4eaf40d0a52ec 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -44,6 +44,7 @@ config RISCV > > select ARCH_HAS_UBSAN > > select ARCH_HAS_VDSO_DATA > > select ARCH_KEEP_MEMBLOCK if ACPI > > + select ARCH_NEED_CMPXCHG_1_2_EMU > > select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX > > select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT > > select ARCH_STACKWALK > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > > index 2fee65cc84432..a5b377481785c 100644 > > --- a/arch/riscv/include/asm/cmpxchg.h > > +++ b/arch/riscv/include/asm/cmpxchg.h > > @@ -9,6 +9,7 @@ > > #include <linux/bug.h> > > > > #include <asm/fence.h> > > +#include <linux/cmpxchg-emu.h> > > > > #define __xchg_relaxed(ptr, new, size) \ > > ({ \ > > @@ -170,6 +171,12 @@ > > __typeof__(*(ptr)) __ret; \ > > register unsigned int __rc; \ > > switch (size) { \ > > + case 1: \ > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > + break; \ > > + case 2: \ > > + break; \ > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > case 4: \ > > __asm__ __volatile__ ( \ > > "0: lr.w %0, %2\n" \ > > @@ -214,6 +221,12 @@ > > __typeof__(*(ptr)) __ret; \ > > register unsigned int __rc; \ > > switch (size) { \ > > + case 1: \ > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > + break; \ > > + case 2: \ > > + break; \ > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > case 4: \ > > __asm__ __volatile__ ( \ > > "0: lr.w %0, %2\n" \ > > @@ -260,6 +273,12 @@ > > __typeof__(*(ptr)) __ret; \ > > register unsigned int __rc; \ > > switch (size) { \ > > + case 1: \ > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > + break; \ > > + case 2: \ > > + break; \ > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > case 4: \ > > __asm__ __volatile__ ( \ > > RISCV_RELEASE_BARRIER \ > > @@ -306,6 +325,12 @@ > > __typeof__(*(ptr)) __ret; \ > > register unsigned int __rc; \ > > switch (size) { \ > > + case 1: \ > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > + break; \ > > + case 2: \ > > + break; \ > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > case 4: \ > > __asm__ __volatile__ ( \ > > "0: lr.w %0, %2\n" \ > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and two-byte cmpxchg 2024-05-11 6:50 ` Guo Ren @ 2024-05-11 14:54 ` Paul E. McKenney 2024-05-11 20:44 ` Leonardo Bras 0 siblings, 1 reply; 6+ messages in thread From: Paul E. McKenney @ 2024-05-11 14:54 UTC (permalink / raw) To: Guo Ren Cc: Leonardo Bras, linux-kernel, kernel-team, andi.shyti, andrzej.hajda, linux-riscv, palmer On Sat, May 11, 2024 at 02:50:13AM -0400, Guo Ren wrote: > On Thu, Apr 04, 2024 at 07:15:40AM -0700, Palmer Dabbelt wrote: > > On Mon, 01 Apr 2024 14:39:50 PDT (-0700), paulmck@kernel.org wrote: > > > Use the new cmpxchg_emu_u8() and cmpxchg_emu_u16() to emulate one-byte > > > and two-byte cmpxchg() on riscv. > > > > > > [ paulmck: Apply kernel test robot feedback. ] > > > > I'm not entirely following the thread, but sounds like there's going to be > > generic kernel users of this now? Before we'd said "no" to the byte/half > > atomic emulation routines beacuse they weren't used, but if it's a generic > > thing then I'm find adding them. > > > > There's a patch set over here > > <https://lore.kernel.org/all/20240103163203.72768-2-leobras@redhat.com/> > > that implements these more directly using LR/SC. I was sort of on the fence > > about just taking it even with no direct users right now, as the byte/half > > atomic extension is working its way through the spec process so we'll have > > them for real soon. I stopped right there for the last merge window, > > though, as I figured it was too late to be messing with the atomics... > > > > So > > > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > F.Y.I Leonardo Bras <leobras@redhat.com> I am carrying this in -rcu, but only for testing purposes, not for inclusion into mainline. Not that I know of anyone testing -rcu on RISC-V, but still, I wouldn't want to do anything do discourage such testing. The reason that this patch is no longer intended for inclusion is that it has been obsoleted by a patch that provides native support for one-byte and two-byte cmpxchg() operations. Which is even better! ;-) Thanx, Paul > > if you guys want to take some sort of tree-wide change to make the byte/half > > stuff be required everywhere. We'll eventually end up with arch routines > > for the extension, so at that point we might as well also have the more > > direct LR/SC flavors. > > > > If you want I can go review/merge that RISC-V patch set and then it'll have > > time to bake for a shared tag you can pick up for all this stuff? No rush > > on my end, just LMK. > > > > > Signed-off-by: Paul E. McKenney <paulmck@kernel.org> > > > Cc: Andi Shyti <andi.shyti@linux.intel.com> > > > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > > > Cc: <linux-riscv@lists.infradead.org> > > > --- > > > arch/riscv/Kconfig | 1 + > > > arch/riscv/include/asm/cmpxchg.h | 25 +++++++++++++++++++++++++ > > > 2 files changed, 26 insertions(+) > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > > index be09c8836d56b..4eaf40d0a52ec 100644 > > > --- a/arch/riscv/Kconfig > > > +++ b/arch/riscv/Kconfig > > > @@ -44,6 +44,7 @@ config RISCV > > > select ARCH_HAS_UBSAN > > > select ARCH_HAS_VDSO_DATA > > > select ARCH_KEEP_MEMBLOCK if ACPI > > > + select ARCH_NEED_CMPXCHG_1_2_EMU > > > select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX > > > select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT > > > select ARCH_STACKWALK > > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > > > index 2fee65cc84432..a5b377481785c 100644 > > > --- a/arch/riscv/include/asm/cmpxchg.h > > > +++ b/arch/riscv/include/asm/cmpxchg.h > > > @@ -9,6 +9,7 @@ > > > #include <linux/bug.h> > > > > > > #include <asm/fence.h> > > > +#include <linux/cmpxchg-emu.h> > > > > > > #define __xchg_relaxed(ptr, new, size) \ > > > ({ \ > > > @@ -170,6 +171,12 @@ > > > __typeof__(*(ptr)) __ret; \ > > > register unsigned int __rc; \ > > > switch (size) { \ > > > + case 1: \ > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > + break; \ > > > + case 2: \ > > > + break; \ > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > case 4: \ > > > __asm__ __volatile__ ( \ > > > "0: lr.w %0, %2\n" \ > > > @@ -214,6 +221,12 @@ > > > __typeof__(*(ptr)) __ret; \ > > > register unsigned int __rc; \ > > > switch (size) { \ > > > + case 1: \ > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > + break; \ > > > + case 2: \ > > > + break; \ > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > case 4: \ > > > __asm__ __volatile__ ( \ > > > "0: lr.w %0, %2\n" \ > > > @@ -260,6 +273,12 @@ > > > __typeof__(*(ptr)) __ret; \ > > > register unsigned int __rc; \ > > > switch (size) { \ > > > + case 1: \ > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > + break; \ > > > + case 2: \ > > > + break; \ > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > case 4: \ > > > __asm__ __volatile__ ( \ > > > RISCV_RELEASE_BARRIER \ > > > @@ -306,6 +325,12 @@ > > > __typeof__(*(ptr)) __ret; \ > > > register unsigned int __rc; \ > > > switch (size) { \ > > > + case 1: \ > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > + break; \ > > > + case 2: \ > > > + break; \ > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > case 4: \ > > > __asm__ __volatile__ ( \ > > > "0: lr.w %0, %2\n" \ > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and two-byte cmpxchg 2024-05-11 14:54 ` Paul E. McKenney @ 2024-05-11 20:44 ` Leonardo Bras 0 siblings, 0 replies; 6+ messages in thread From: Leonardo Bras @ 2024-05-11 20:44 UTC (permalink / raw) To: Paul E. McKenney Cc: Leonardo Bras, Guo Ren, linux-kernel, kernel-team, andi.shyti, andrzej.hajda, linux-riscv, palmer On Sat, May 11, 2024 at 07:54:34AM -0700, Paul E. McKenney wrote: > On Sat, May 11, 2024 at 02:50:13AM -0400, Guo Ren wrote: > > On Thu, Apr 04, 2024 at 07:15:40AM -0700, Palmer Dabbelt wrote: > > > On Mon, 01 Apr 2024 14:39:50 PDT (-0700), paulmck@kernel.org wrote: > > > > Use the new cmpxchg_emu_u8() and cmpxchg_emu_u16() to emulate one-byte > > > > and two-byte cmpxchg() on riscv. > > > > > > > > [ paulmck: Apply kernel test robot feedback. ] > > > > > > I'm not entirely following the thread, but sounds like there's going to be > > > generic kernel users of this now? Before we'd said "no" to the byte/half > > > atomic emulation routines beacuse they weren't used, but if it's a generic > > > thing then I'm find adding them. > > > > > > There's a patch set over here > > > <https://lore.kernel.org/all/20240103163203.72768-2-leobras@redhat.com/> > > > that implements these more directly using LR/SC. I was sort of on the fence > > > about just taking it even with no direct users right now, as the byte/half > > > atomic extension is working its way through the spec process so we'll have > > > them for real soon. I stopped right there for the last merge window, > > > though, as I figured it was too late to be messing with the atomics... > > > > > > So > > > > > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > F.Y.I Leonardo Bras <leobras@redhat.com> Hi Guo Ren, thanks for bringing it to my attention. I am quite excited about the inclusion of my patchset on riscv/cmpxchg, and I hope it can be useful both to your qspinlock implementation and on Paul's RCU improvement. > > I am carrying this in -rcu, but only for testing purposes, not for > inclusion into mainline. Not that I know of anyone testing -rcu on > RISC-V, but still, I wouldn't want to do anything do discourage such > testing. > > The reason that this patch is no longer intended for inclusion is that it > has been obsoleted by a patch that provides native support for one-byte > and two-byte cmpxchg() operations. Which is even better! ;-) > > Thanx, Paul Thanks Paul! Months ago I have reworked cmpxchg and added those 1-byte and 2-byte {cmp,}xchg asm implementations using lr/sc, as they would be useful to Guo Ren's qspinlock, and I am thankful that you provided another use case, because it provides more proof of it's usefulness. Thanks! Leo > > > > if you guys want to take some sort of tree-wide change to make the byte/half > > > stuff be required everywhere. We'll eventually end up with arch routines > > > for the extension, so at that point we might as well also have the more > > > direct LR/SC flavors. > > > > > > If you want I can go review/merge that RISC-V patch set and then it'll have > > > time to bake for a shared tag you can pick up for all this stuff? No rush > > > on my end, just LMK. > > > > > > > Signed-off-by: Paul E. McKenney <paulmck@kernel.org> > > > > Cc: Andi Shyti <andi.shyti@linux.intel.com> > > > > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > > > > Cc: <linux-riscv@lists.infradead.org> > > > > --- > > > > arch/riscv/Kconfig | 1 + > > > > arch/riscv/include/asm/cmpxchg.h | 25 +++++++++++++++++++++++++ > > > > 2 files changed, 26 insertions(+) > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > > > index be09c8836d56b..4eaf40d0a52ec 100644 > > > > --- a/arch/riscv/Kconfig > > > > +++ b/arch/riscv/Kconfig > > > > @@ -44,6 +44,7 @@ config RISCV > > > > select ARCH_HAS_UBSAN > > > > select ARCH_HAS_VDSO_DATA > > > > select ARCH_KEEP_MEMBLOCK if ACPI > > > > + select ARCH_NEED_CMPXCHG_1_2_EMU > > > > select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX > > > > select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT > > > > select ARCH_STACKWALK > > > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > > > > index 2fee65cc84432..a5b377481785c 100644 > > > > --- a/arch/riscv/include/asm/cmpxchg.h > > > > +++ b/arch/riscv/include/asm/cmpxchg.h > > > > @@ -9,6 +9,7 @@ > > > > #include <linux/bug.h> > > > > > > > > #include <asm/fence.h> > > > > +#include <linux/cmpxchg-emu.h> > > > > > > > > #define __xchg_relaxed(ptr, new, size) \ > > > > ({ \ > > > > @@ -170,6 +171,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > "0: lr.w %0, %2\n" \ > > > > @@ -214,6 +221,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > "0: lr.w %0, %2\n" \ > > > > @@ -260,6 +273,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > RISCV_RELEASE_BARRIER \ > > > > @@ -306,6 +325,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > "0: lr.w %0, %2\n" \ > > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 6+ messages in thread
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[not found] <31c82dcc-e203-48a9-aadd-f2fcd57d94c1@paulmck-laptop>
2024-04-01 21:39 ` [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and two-byte cmpxchg Paul E. McKenney
2024-04-04 14:15 ` Palmer Dabbelt
2024-04-04 14:50 ` Paul E. McKenney
2024-05-11 6:50 ` Guo Ren
2024-05-11 14:54 ` Paul E. McKenney
2024-05-11 20:44 ` Leonardo Bras
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