* [PATCH 2/2 v2] RISC-V: add Star64 board devicetree
@ 2024-05-23 21:55 Henry Bell
2024-05-27 17:58 ` Conor Dooley
0 siblings, 1 reply; 2+ messages in thread
From: Henry Bell @ 2024-05-23 21:55 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
The Pine64 Star64 is a development board based on the Starfive JH7110 SoC.
The board features:
- JH7110 SoC
- 4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x eMMC slot
- 1x MicroSD slot
- 1x QSPI Flash
- 2x 1Gbps Ethernet port
- 1x HDMI port
- 1x 4-lane DSI
- 1x 2-lane CSI
- 1x PCIe 2.0 x1 lane
Signed-off-by: Henry Bell <dmoo_dv@protonmail.com>
---
Changes since v1:
- Fix indentation and issues with field ordering
- Update Copyright
- Move from patch 1 to patch 2
---
arch/riscv/boot/dts/starfive/Makefile | 1 +
.../dts/starfive/jh7110-pine64-star64.dts | 61 +++++++++++++++++++
2 files changed, 62 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 2fa0cd7f31c3..7a163a7d6ba3 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
new file mode 100644
index 000000000000..fe7e5f3f7f23
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Henry Bell <dmoo_dv@protonmail.com>
+ */
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+/ {
+ model = "Pine64 Star64";
+ compatible = "pine64,star64", "starfive,jh7110";
+ aliases {
+ ethernet1 = &gmac1;
+ };
+};
+
+&gmac0 {
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+ assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+};
+
+&gmac1 {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
+
+&phy0 {
+ rx-internal-delay-ps = <1900>;
+ tx-internal-delay-ps = <1500>;
+ motorcomm,rx-clk-drv-microamp = <2910>;
+ motorcomm,rx-data-drv-microamp = <2910>;
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-10-inverted;
+ motorcomm,tx-clk-100-inverted;
+ motorcomm,tx-clk-1000-inverted;
+};
+
+&phy1 {
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <300>;
+ motorcomm,rx-clk-drv-microamp = <2910>;
+ motorcomm,rx-data-drv-microamp = <2910>;
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-10-inverted;
+ motorcomm,tx-clk-100-inverted;
+};
--
2.44.0
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 2/2 v2] RISC-V: add Star64 board devicetree
2024-05-23 21:55 [PATCH 2/2 v2] RISC-V: add Star64 board devicetree Henry Bell
@ 2024-05-27 17:58 ` Conor Dooley
0 siblings, 0 replies; 2+ messages in thread
From: Conor Dooley @ 2024-05-27 17:58 UTC (permalink / raw)
To: Henry Bell
Cc: Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
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On Thu, May 23, 2024 at 09:55:38PM +0000, Henry Bell wrote:
> The Pine64 Star64 is a development board based on the Starfive JH7110 SoC.
> The board features:
>
> - JH7110 SoC
> - 4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 1x USB 3.0 host port
> - 3x USB 2.0 host port
> - 1x eMMC slot
> - 1x MicroSD slot
> - 1x QSPI Flash
> - 2x 1Gbps Ethernet port
> - 1x HDMI port
> - 1x 4-lane DSI
> - 1x 2-lane CSI
> - 1x PCIe 2.0 x1 lane
>
> Signed-off-by: Henry Bell <dmoo_dv@protonmail.com>
> ---
>
> Changes since v1:
>
> - Fix indentation and issues with field ordering
> - Update Copyright
> - Move from patch 1 to patch 2
> ---
> arch/riscv/boot/dts/starfive/Makefile | 1 +
> .../dts/starfive/jh7110-pine64-star64.dts | 61 +++++++++++++++++++
> 2 files changed, 62 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
>
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 2fa0cd7f31c3..7a163a7d6ba3 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
>
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
> +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> new file mode 100644
> index 000000000000..fe7e5f3f7f23
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Henry Bell <dmoo_dv@protonmail.com>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-common.dtsi"
> +
> +/ {
> + model = "Pine64 Star64";
> + compatible = "pine64,star64", "starfive,jh7110";
> + aliases {
> + ethernet1 = &gmac1;
> + };
There was still some funky looking indentation here, so I fixed that up
on application.
Emil, shout if you spot something awry, it's gonna be at the top of the
branch for a while I bet so plenty of time to drop etc.
Thanks,
Conor.
> +};
> +
> +&gmac0 {
> + starfive,tx-use-rgmii-clk;
> + assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
> + assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
> +};
> +
> +&gmac1 {
> + phy-handle = <&phy1>;
> + phy-mode = "rgmii-id";
> + starfive,tx-use-rgmii-clk;
> + assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
> + assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> +
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> + };
> +};
> +
> +&phy0 {
> + rx-internal-delay-ps = <1900>;
> + tx-internal-delay-ps = <1500>;
> + motorcomm,rx-clk-drv-microamp = <2910>;
> + motorcomm,rx-data-drv-microamp = <2910>;
> + motorcomm,tx-clk-adj-enabled;
> + motorcomm,tx-clk-10-inverted;
> + motorcomm,tx-clk-100-inverted;
> + motorcomm,tx-clk-1000-inverted;
> +};
> +
> +&phy1 {
> + rx-internal-delay-ps = <0>;
> + tx-internal-delay-ps = <300>;
> + motorcomm,rx-clk-drv-microamp = <2910>;
> + motorcomm,rx-data-drv-microamp = <2910>;
> + motorcomm,tx-clk-adj-enabled;
> + motorcomm,tx-clk-10-inverted;
> + motorcomm,tx-clk-100-inverted;
> +};
> --
> 2.44.0
>
>
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