From: Chen Wang <unicornxw@gmail.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, inochiama@outlook.com,
conor.dooley@microchip.com, guoren@kernel.org,
emil.renner.berthing@canonical.com, apatel@ventanamicro.com,
hal.feng@starfivetech.com, dfustini@baylibre.com,
prabhakar.mahadev-lad.rj@bp.renesas.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com
Cc: Chen Wang <unicorn_wang@outlook.com>
Subject: [PATCH] riscv: defconfig: sophgo: enable clks for sg2042
Date: Mon, 5 Aug 2024 10:33:20 +0800 [thread overview]
Message-ID: <20240805023320.1287061-1-unicornxw@gmail.com> (raw)
From: Chen Wang <unicorn_wang@outlook.com>
Enable clk generators for sg2042 due to many peripherals rely on
these clocks.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 0d678325444f..d43a028909e5 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -249,6 +249,9 @@ CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
CONFIG_CLK_SOPHGO_CV1800=y
+CONFIG_CLK_SOPHGO_SG2042_PLL=y
+CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y
+CONFIG_CLK_SOPHGO_SG2042_RPGATE=y
CONFIG_SUN8I_DE2_CCU=m
CONFIG_RENESAS_OSTM=y
CONFIG_SUN50I_IOMMU=y
base-commit: de9c2c66ad8e787abec7c9d7eff4f8c3cdd28aed
--
2.34.1
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next reply other threads:[~2024-08-05 2:33 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-05 2:33 Chen Wang [this message]
2024-08-06 9:30 ` [PATCH] riscv: defconfig: sophgo: enable clks for sg2042 Emil Renner Berthing
2024-08-07 0:45 ` Chen Wang
2024-08-09 6:26 ` Chen Wang
2024-08-15 0:09 ` Chen Wang
2024-08-19 17:02 ` Conor Dooley
2024-08-19 23:49 ` Chen Wang
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