From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Samuel Holland <samuel.holland@sifive.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>,
Andy Chiu <andy.chiu@sifive.com>,
Jessica Clarke <jrtc27@jrtc27.com>,
Andrew Jones <ajones@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v9 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
Date: Tue, 06 Aug 2024 17:31:39 -0700 [thread overview]
Message-ID: <20240806-xtheadvector-v9-3-62a56d2da5d0@rivosinc.com> (raw)
In-Reply-To: <20240806-xtheadvector-v9-0-62a56d2da5d0@rivosinc.com>
The D1/D1s SoCs support xtheadvector so it can be included in the
devicetree. Also include vlenb for the cpu.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 64c3c2e6cbe0..6367112e614a 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -27,7 +27,8 @@ cpu0: cpu@0 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
+ "zifencei", "zihpm", "xtheadvector";
+ thead,vlenb = <128>;
#cooling-cells = <2>;
cpu0_intc: interrupt-controller {
--
2.45.0
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next prev parent reply other threads:[~2024-08-07 0:31 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-07 0:31 [PATCH v9 00/13] riscv: Add support for xtheadvector Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 02/13] dt-bindings: cpus: add a thead vlen register length property Charlie Jenkins
2024-08-07 0:31 ` Charlie Jenkins [this message]
2024-08-07 0:31 ` [PATCH v9 04/13] riscv: Add thead and xtheadvector as a vendor extension Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 05/13] riscv: vector: Use vlenb from DT for thead Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 06/13] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 07/13] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 08/13] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 09/13] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 10/13] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 12/13] selftests: riscv: Fix vector tests Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 13/13] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-08-09 22:31 ` [PATCH v9 00/13] riscv: Add support for xtheadvector Conor Dooley
2024-08-13 0:45 ` Charlie Jenkins
2024-08-13 15:55 ` Conor Dooley
2024-08-19 23:06 ` Charlie Jenkins
2024-08-20 16:42 ` Conor Dooley
2024-08-10 18:58 ` indrek.kruusa
2024-08-19 23:08 ` Charlie Jenkins
2024-08-21 15:41 ` indrek.kruusa
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