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From: indrek.kruusa@gmail.com
To: charlie@rivosinc.com
Cc: apatel@ventanamicro.com, conor.dooley@microchip.com,
	guoren@kernel.org, heiko@sntech.de, jernej.skrabec@gmail.com,
	linux-riscv@lists.infradead.org, samuel.holland@sifive.com,
	samuel@sholland.org
Subject: Re: [PATCH v9 00/13] riscv: Add support for xtheadvector
Date: Wed, 21 Aug 2024 18:41:27 +0300	[thread overview]
Message-ID: <20240821154127.105-1-indrek.kruusa@gmail.com> (raw)
In-Reply-To: <ZsPQVpJAh7L5kuXX@ghost>

> Anup sent out a patch to fix this:
> https://lore.kernel.org/lkml/20240817081218.2985171-1-apatel@ventanamicro.com/.

Thank you for the feedback! As I'm seeing now from related e-mail threads then
the issue was reported quite a while back. Obviously I didn't dig deep enough
in linux-riscv archives and started to kind of bisect the issue by my self.
It's sad to read about how Allwinner doesn't provide much or any resources to
maintain the sofware support for its own chips. The next problem I have with
this CPU (D1s actually) is that u-boot compiled with binutils newer than v2.40
will not boot. But that's another story.


Thank you. I appreciate your help.
Indrek

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      reply	other threads:[~2024-08-21 16:09 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-07  0:31 [PATCH v9 00/13] riscv: Add support for xtheadvector Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 02/13] dt-bindings: cpus: add a thead vlen register length property Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 04/13] riscv: Add thead and xtheadvector as a vendor extension Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 05/13] riscv: vector: Use vlenb from DT for thead Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 06/13] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 07/13] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 08/13] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 09/13] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 10/13] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 12/13] selftests: riscv: Fix vector tests Charlie Jenkins
2024-08-07  0:31 ` [PATCH v9 13/13] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-08-09 22:31 ` [PATCH v9 00/13] riscv: Add support for xtheadvector Conor Dooley
2024-08-13  0:45   ` Charlie Jenkins
2024-08-13 15:55     ` Conor Dooley
2024-08-19 23:06       ` Charlie Jenkins
2024-08-20 16:42         ` Conor Dooley
2024-08-10 18:58 ` indrek.kruusa
2024-08-19 23:08   ` Charlie Jenkins
2024-08-21 15:41     ` indrek.kruusa [this message]

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