* [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3
@ 2024-09-15 14:45 Jesse Taube
2024-09-16 2:45 ` Yixun Lan
0 siblings, 1 reply; 5+ messages in thread
From: Jesse Taube @ 2024-09-15 14:45 UTC (permalink / raw)
To: Yixun Lan
Cc: devicetree, Conor Dooley, Albert Ou, Yixun Lan,
Krzysztof Kozlowski, linux-gpio, Linus Walleij, linux-kernel,
Conor Dooley, Yangyu Chen, Palmer Dabbelt, Meng Zhang,
Jisheng Zhang, Paul Walmsley, Inochi Amaoto, linux-riscv,
Rob Herring, Meng Zhang
Before pinctrl driver implemented, the uart0 controller reply on
bootloader for setting correct pin mux and configurations.
Now, let's add pinctrl property to uart0 of Bananapi-F3 board.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 3 +++
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 ++++++++++++++++++++
arch/riscv/boot/dts/spacemit/k1.dtsi | 5 +++++
3 files changed, 28 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 023274189b492..bc88d4de25a62 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -4,6 +4,7 @@
*/
#include "k1.dtsi"
+#include "k1-pinctrl.dtsi"
/ {
model = "Banana Pi BPI-F3";
@@ -15,5 +16,7 @@ chosen {
};
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
new file mode 100644
index 0000000000000..a8eac5517f857
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
It would be nice to have a pinfunc header like
arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h.
It would reference and encode the data of "3.2 Pin Multiplex" in
https://developer.spacemit.com/documentation?token=An1vwTwKaigaXRkYfwmcznTXned
, the document you attached in the summary.
Otherwise,
Acked-by: Jesse Taube <Mr.Bossman075@gmail.com>
+
+&pinctrl {
+ uart0_2_cfg: uart0-2-cfg {
+ uart0-2-pins {
+ pinmux = <K1_PADCONF(68, 2)>,
+ <K1_PADCONF(69, 2)>;
+
+ bias-pull-up = <0>;
+ drive-strength = <32>;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi
b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 0777bf9e01183..a2d5f7d4a942a 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -416,6 +416,11 @@ uart9: serial@d4017800 {
status = "disabled";
};
+ pinctrl: pinctrl@d401e000 {
+ compatible = "spacemit,k1-pinctrl";
+ reg = <0x0 0xd401e000 0x0 0x400>;
+ };
+
plic: interrupt-controller@e0000000 {
compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
reg = <0x0 0xe0000000 0x0 0x4000000>;
--
2.45.2
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3
2024-09-15 14:45 [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3 Jesse Taube
@ 2024-09-16 2:45 ` Yixun Lan
2024-09-16 14:18 ` Jesse T
0 siblings, 1 reply; 5+ messages in thread
From: Yixun Lan @ 2024-09-16 2:45 UTC (permalink / raw)
To: Jesse Taube
Cc: devicetree, Conor Dooley, Albert Ou, Krzysztof Kozlowski,
linux-gpio, Linus Walleij, linux-kernel, Conor Dooley,
Yangyu Chen, Palmer Dabbelt, Meng Zhang, Jisheng Zhang,
Paul Walmsley, Inochi Amaoto, linux-riscv, Rob Herring,
Meng Zhang
Hi Jesse
On 10:45 Sun 15 Sep , Jesse Taube wrote:
>
> Before pinctrl driver implemented, the uart0 controller reply on
> bootloader for setting correct pin mux and configurations.
>
> Now, let's add pinctrl property to uart0 of Bananapi-F3 board.
>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> ---
> arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 3 +++
> arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 ++++++++++++++++++++
> arch/riscv/boot/dts/spacemit/k1.dtsi | 5 +++++
> 3 files changed, 28 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> index 023274189b492..bc88d4de25a62 100644
> --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> @@ -4,6 +4,7 @@
> */
>
> #include "k1.dtsi"
> +#include "k1-pinctrl.dtsi"
>
> / {
> model = "Banana Pi BPI-F3";
> @@ -15,5 +16,7 @@ chosen {
> };
>
> &uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_2_cfg>;
> status = "okay";
> };
> diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> new file mode 100644
> index 0000000000000..a8eac5517f857
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
>
> It would be nice to have a pinfunc header like
> arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h.
> It would reference and encode the data of "3.2 Pin Multiplex" in
> https://developer.spacemit.com/documentation?token=An1vwTwKaigaXRkYfwmcznTXned
> , the document you attached in the summary.
Not sure if it's worth the effort..
I gave up of introducing another macro, as it's exactly one to one mapping to
GPIO ID, which mean pin(x) -> GPIO_x
maybe I could put a comment at K1_PADCONF() to document this?
/* pin is same to the GPIO id according to 3.2 Pin Multiplex of User Manual */
#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
does this sound good to you?
>
> Otherwise,
> Acked-by: Jesse Taube <Mr.Bossman075@gmail.com>
>
thanks
> +
> +&pinctrl {
> + uart0_2_cfg: uart0-2-cfg {
> + uart0-2-pins {
> + pinmux = <K1_PADCONF(68, 2)>,
> + <K1_PADCONF(69, 2)>;
> +
> + bias-pull-up = <0>;
> + drive-strength = <32>;
> + };
> + };
> +};
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi
> b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index 0777bf9e01183..a2d5f7d4a942a 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -416,6 +416,11 @@ uart9: serial@d4017800 {
> status = "disabled";
> };
>
> + pinctrl: pinctrl@d401e000 {
> + compatible = "spacemit,k1-pinctrl";
> + reg = <0x0 0xd401e000 0x0 0x400>;
> + };
> +
> plic: interrupt-controller@e0000000 {
> compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> reg = <0x0 0xe0000000 0x0 0x4000000>;
>
> --
> 2.45.2
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3
2024-09-16 2:45 ` Yixun Lan
@ 2024-09-16 14:18 ` Jesse T
2024-09-16 23:47 ` Yixun Lan
0 siblings, 1 reply; 5+ messages in thread
From: Jesse T @ 2024-09-16 14:18 UTC (permalink / raw)
To: Yixun Lan
Cc: devicetree, Conor Dooley, Albert Ou, Krzysztof Kozlowski,
linux-gpio, Linus Walleij, linux-kernel, Conor Dooley,
Yangyu Chen, Palmer Dabbelt, Meng Zhang, Jisheng Zhang,
Paul Walmsley, Inochi Amaoto, linux-riscv, Rob Herring,
Meng Zhang
On Sun, Sep 15, 2024 at 10:45 PM Yixun Lan <dlan@gentoo.org> wrote:
>
> Hi Jesse
>
> On 10:45 Sun 15 Sep , Jesse Taube wrote:
> >
> > Before pinctrl driver implemented, the uart0 controller reply on
> > bootloader for setting correct pin mux and configurations.
> >
> > Now, let's add pinctrl property to uart0 of Bananapi-F3 board.
> >
> > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > ---
> > arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 3 +++
> > arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 ++++++++++++++++++++
> > arch/riscv/boot/dts/spacemit/k1.dtsi | 5 +++++
> > 3 files changed, 28 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > index 023274189b492..bc88d4de25a62 100644
> > --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > @@ -4,6 +4,7 @@
> > */
> >
> > #include "k1.dtsi"
> > +#include "k1-pinctrl.dtsi"
> >
> > / {
> > model = "Banana Pi BPI-F3";
> > @@ -15,5 +16,7 @@ chosen {
> > };
> >
> > &uart0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart0_2_cfg>;
> > status = "okay";
> > };
> > diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > new file mode 100644
> > index 0000000000000..a8eac5517f857
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > @@ -0,0 +1,20 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
> > + */
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
> >
> > It would be nice to have a pinfunc header like
> > arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h.
> > It would reference and encode the data of "3.2 Pin Multiplex" in
> > https://developer.spacemit.com/documentation?token=An1vwTwKaigaXRkYfwmcznTXned
> > , the document you attached in the summary.
> Not sure if it's worth the effort..
I can send a future patch for this.
>
> I gave up of introducing another macro, as it's exactly one to one mapping to
> GPIO ID, which mean pin(x) -> GPIO_x
>
> maybe I could put a comment at K1_PADCONF() to document this?
I'm weary the Manual may not exist on the site in the future or
will change formats. But it would be nice otherwise.
>
> /* pin is same to the GPIO id according to 3.2 Pin Multiplex of User Manual */
> #define K1_PADCONF(pin, func) (((pin) << 16) | (func))
>
> does this sound good to you?
Sure, add it.
Also sorry for messing up the reply-to thing thunderbird is confusing.
Thanks,
Jesse Taube
>
> >
> > Otherwise,
> > Acked-by: Jesse Taube <Mr.Bossman075@gmail.com>
> >
> thanks
>
> > +
> > +&pinctrl {
> > + uart0_2_cfg: uart0-2-cfg {
> > + uart0-2-pins {
> > + pinmux = <K1_PADCONF(68, 2)>,
> > + <K1_PADCONF(69, 2)>;
> > +
> > + bias-pull-up = <0>;
> > + drive-strength = <32>;
> > + };
> > + };
> > +};
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi
> > b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > index 0777bf9e01183..a2d5f7d4a942a 100644
> > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > @@ -416,6 +416,11 @@ uart9: serial@d4017800 {
> > status = "disabled";
> > };
> >
> > + pinctrl: pinctrl@d401e000 {
> > + compatible = "spacemit,k1-pinctrl";
> > + reg = <0x0 0xd401e000 0x0 0x400>;
> > + };
> > +
> > plic: interrupt-controller@e0000000 {
> > compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> > reg = <0x0 0xe0000000 0x0 0x4000000>;
> >
> > --
> > 2.45.2
>
> --
> Yixun Lan (dlan)
> Gentoo Linux Developer
> GPG Key ID AABEFD55
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3
2024-09-16 14:18 ` Jesse T
@ 2024-09-16 23:47 ` Yixun Lan
0 siblings, 0 replies; 5+ messages in thread
From: Yixun Lan @ 2024-09-16 23:47 UTC (permalink / raw)
To: Jesse T
Cc: devicetree, Conor Dooley, Albert Ou, Krzysztof Kozlowski,
linux-gpio, Linus Walleij, linux-kernel, Conor Dooley,
Yangyu Chen, Palmer Dabbelt, Meng Zhang, Jisheng Zhang,
Paul Walmsley, Inochi Amaoto, linux-riscv, Rob Herring,
Meng Zhang
Hi Jesse:
On 10:18 Mon 16 Sep , Jesse T wrote:
> On Sun, Sep 15, 2024 at 10:45 PM Yixun Lan <dlan@gentoo.org> wrote:
> >
> > Hi Jesse
> >
> > On 10:45 Sun 15 Sep , Jesse Taube wrote:
> > >
> > > Before pinctrl driver implemented, the uart0 controller reply on
> > > bootloader for setting correct pin mux and configurations.
> > >
> > > Now, let's add pinctrl property to uart0 of Bananapi-F3 board.
> > >
> > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > ---
> > > arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 3 +++
> > > arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 ++++++++++++++++++++
> > > arch/riscv/boot/dts/spacemit/k1.dtsi | 5 +++++
> > > 3 files changed, 28 insertions(+)
> > >
> > > diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > > b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > > index 023274189b492..bc88d4de25a62 100644
> > > --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > > +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > > @@ -4,6 +4,7 @@
> > > */
> > >
> > > #include "k1.dtsi"
> > > +#include "k1-pinctrl.dtsi"
> > >
> > > / {
> > > model = "Banana Pi BPI-F3";
> > > @@ -15,5 +16,7 @@ chosen {
> > > };
> > >
> > > &uart0 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&uart0_2_cfg>;
> > > status = "okay";
> > > };
> > > diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > > b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > > new file mode 100644
> > > index 0000000000000..a8eac5517f857
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > > @@ -0,0 +1,20 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
> > > + */
> > > +
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +
> > > +#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
> > >
> > > It would be nice to have a pinfunc header like
> > > arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h.
> > > It would reference and encode the data of "3.2 Pin Multiplex" in
> > > https://developer.spacemit.com/documentation?token=An1vwTwKaigaXRkYfwmcznTXned
> > > , the document you attached in the summary.
> > Not sure if it's worth the effort..
>
> I can send a future patch for this.
>
Ok, thanks, no objection from my side
but, that gonna be a lot work as you need to list ALL the functions..
> >
> > I gave up of introducing another macro, as it's exactly one to one mapping to
> > GPIO ID, which mean pin(x) -> GPIO_x
> >
> > maybe I could put a comment at K1_PADCONF() to document this?
>
> I'm weary the Manual may not exist on the site in the future or
> will change formats. But it would be nice otherwise.
>
> >
> > /* pin is same to the GPIO id according to 3.2 Pin Multiplex of User Manual */
> > #define K1_PADCONF(pin, func) (((pin) << 16) | (func))
> >
> > does this sound good to you?
>
> Sure, add it.
>
> Also sorry for messing up the reply-to thing thunderbird is confusing.
>
> Thanks,
> Jesse Taube
>
> >
> > >
> > > Otherwise,
> > > Acked-by: Jesse Taube <Mr.Bossman075@gmail.com>
> > >
> > thanks
> >
> > > +
> > > +&pinctrl {
> > > + uart0_2_cfg: uart0-2-cfg {
> > > + uart0-2-pins {
> > > + pinmux = <K1_PADCONF(68, 2)>,
> > > + <K1_PADCONF(69, 2)>;
> > > +
> > > + bias-pull-up = <0>;
> > > + drive-strength = <32>;
> > > + };
> > > + };
> > > +};
> > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > index 0777bf9e01183..a2d5f7d4a942a 100644
> > > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > @@ -416,6 +416,11 @@ uart9: serial@d4017800 {
> > > status = "disabled";
> > > };
> > >
> > > + pinctrl: pinctrl@d401e000 {
> > > + compatible = "spacemit,k1-pinctrl";
> > > + reg = <0x0 0xd401e000 0x0 0x400>;
> > > + };
> > > +
> > > plic: interrupt-controller@e0000000 {
> > > compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> > > reg = <0x0 0xe0000000 0x0 0x4000000>;
> > >
> > > --
> > > 2.45.2
> >
> > --
> > Yixun Lan (dlan)
> > Gentoo Linux Developer
> > GPG Key ID AABEFD55
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 0/3] riscv: spacemit: add pinctrl support to K1 SoC
@ 2024-09-03 12:26 Yixun Lan
2024-09-03 12:26 ` [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3 Yixun Lan
0 siblings, 1 reply; 5+ messages in thread
From: Yixun Lan @ 2024-09-03 12:26 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley
Cc: devicetree, Yixun Lan, linux-gpio, linux-kernel, Yangyu Chen,
Meng Zhang, Jisheng Zhang, Inochi Amaoto, linux-riscv, Meng Zhang
This series adds pinctrl support to SpacemiT's K1 SoC, the controller
uses a single register to describe all pin functions, including
bias pull up/down, drive strength, schmitter trigger, slew rate,
strong pull-up, mux mode. In patch #3, we add the pinctrl property of
uart device for the Bananapi-F3 board.
You can find the pinctrl docs of K1 here[1], and the original vendor's
pinctrl dts data here[2].
Note, we rewrite this series as an independent pinctrl driver for K1 SoC,
which means it does not use pinctrl-single driver as the model anymore,
see the suggestion from Krzysztof at [3].
Link: https://developer.spacemit.com/documentation?token=An1vwTwKaigaXRkYfwmcznTXned [1]
Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x_pinctrl.dtsi [2]
Link: https://lore.kernel.org/all/b7a01cba-9f68-4a6f-9795-b9103ee81d8b@kernel.org/ [3]
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
Changes in v4:
- squash dts patch (drop patch #3)
- collect review tags
- Patch #2
- fix pin id mapping
- improve pinconf debugfs
- Link to v3: https://lore.kernel.org/r/20240828-02-k1-pinctrl-v3-0-1fed6a22be98@gentoo.org
Changes in v3:
- dt-bindings: drop vendor specific properties, fix format
- rework pinctrl's gpio request function
- fix logic of slew rate & drive strength
- add power-source check
- improve debugfs info
- Link to v2: https://lore.kernel.org/r/20240825-02-k1-pinctrl-v2-0-ddd38a345d12@gentoo.org
Changes in v2:
- drop using pinctrl-single driver for K1
- rewite as independent pinctrl driver
- rebase to v6.11-rc5
- Link to v1: https://lore.kernel.org/r/20240719-02-k1-pinctrl-v1-0-239ac5b77dd6@gentoo.org
---
Yixun Lan (3):
dt-bindings: pinctrl: spacemit: add support for K1 SoC
pinctrl: spacemit: add support for SpacemiT K1 SoC
riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3
.../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 124 +++
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 3 +
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 +
arch/riscv/boot/dts/spacemit/k1.dtsi | 5 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/spacemit/Kconfig | 17 +
drivers/pinctrl/spacemit/Makefile | 3 +
drivers/pinctrl/spacemit/pinctrl-k1.c | 1078 ++++++++++++++++++++
drivers/pinctrl/spacemit/pinctrl-k1.h | 40 +
10 files changed, 1292 insertions(+)
---
base-commit: 431c1646e1f86b949fa3685efc50b660a364c2b6
change-id: 20240708-02-k1-pinctrl-3a2b0ec13101
prerequisite-change-id: 20240626-k1-01-basic-dt-1aa31eeebcd2:v5
prerequisite-patch-id: 47dcf6861f7d434d25855b379e6d7ef4ce369c9c
prerequisite-patch-id: 77787fe82911923aff15ccf565e8fa451538c3a6
prerequisite-patch-id: b0bdb1742d96c5738f05262c3b0059102761390b
prerequisite-patch-id: 3927d39d8d77e35d5bfe53d9950da574ff8f2054
prerequisite-patch-id: a98039136a4796252a6029e474f03906f2541643
prerequisite-patch-id: c95f6dc0547a2a63a76e3cba0cf5c623b212b4e6
prerequisite-patch-id: 66e750e438ee959ddc2a6f0650814a2d8c989139
prerequisite-patch-id: 29a0fd8c36c1a4340f0d0b68a4c34d2b8abfb1ab
prerequisite-patch-id: 0bdfff661c33c380d1cf00a6c68688e05f88c0b3
prerequisite-patch-id: 99f15718e0bfbb7ed1a96dfa19f35841b004dae9
Best regards,
--
Yixun Lan <dlan@gentoo.org>
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^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3
2024-09-03 12:26 [PATCH v4 0/3] riscv: spacemit: add pinctrl support to K1 SoC Yixun Lan
@ 2024-09-03 12:26 ` Yixun Lan
0 siblings, 0 replies; 5+ messages in thread
From: Yixun Lan @ 2024-09-03 12:26 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley
Cc: devicetree, Yixun Lan, linux-gpio, linux-kernel, Yangyu Chen,
Meng Zhang, Jisheng Zhang, Inochi Amaoto, linux-riscv, Meng Zhang
Before pinctrl driver implemented, the uart0 controller reply on
bootloader for setting correct pin mux and configurations.
Now, let's add pinctrl property to uart0 of Bananapi-F3 board.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 3 +++
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 ++++++++++++++++++++
arch/riscv/boot/dts/spacemit/k1.dtsi | 5 +++++
3 files changed, 28 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 023274189b492..bc88d4de25a62 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -4,6 +4,7 @@
*/
#include "k1.dtsi"
+#include "k1-pinctrl.dtsi"
/ {
model = "Banana Pi BPI-F3";
@@ -15,5 +16,7 @@ chosen {
};
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
new file mode 100644
index 0000000000000..a8eac5517f857
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
+
+&pinctrl {
+ uart0_2_cfg: uart0-2-cfg {
+ uart0-2-pins {
+ pinmux = <K1_PADCONF(68, 2)>,
+ <K1_PADCONF(69, 2)>;
+
+ bias-pull-up = <0>;
+ drive-strength = <32>;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 0777bf9e01183..a2d5f7d4a942a 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -416,6 +416,11 @@ uart9: serial@d4017800 {
status = "disabled";
};
+ pinctrl: pinctrl@d401e000 {
+ compatible = "spacemit,k1-pinctrl";
+ reg = <0x0 0xd401e000 0x0 0x400>;
+ };
+
plic: interrupt-controller@e0000000 {
compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
reg = <0x0 0xe0000000 0x0 0x4000000>;
--
2.45.2
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^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-09-16 23:47 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-09-15 14:45 [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3 Jesse Taube
2024-09-16 2:45 ` Yixun Lan
2024-09-16 14:18 ` Jesse T
2024-09-16 23:47 ` Yixun Lan
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2024-09-03 12:26 [PATCH v4 0/3] riscv: spacemit: add pinctrl support to K1 SoC Yixun Lan
2024-09-03 12:26 ` [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3 Yixun Lan
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