* [PATCH 0/3] riscv: Add bfloat16 instruction support
@ 2024-10-28 7:17 Inochi Amaoto
2024-10-28 7:17 ` [PATCH 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Inochi Amaoto @ 2024-10-28 7:17 UTC (permalink / raw)
To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Clément Léger, Evan Green, Charlie Jenkins,
Andrew Jones, Andy Chiu, Inochi Amaoto, Xiao Wang, Samuel Holland
Cc: linux-doc, linux-riscv, linux-kernel, devicetree
Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.
Inochi Amaoto (3):
dt-bindings: riscv: add bfloat16 ISA extension description
riscv: add ISA extension parsing for bfloat16 ISA extension
riscv: hwprobe: export bfloat16 ISA extension
Documentation/arch/riscv/hwprobe.rst | 12 +++++
.../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++
arch/riscv/include/asm/hwcap.h | 3 ++
arch/riscv/include/uapi/asm/hwprobe.h | 3 ++
arch/riscv/kernel/cpufeature.c | 3 ++
5 files changed, 66 insertions(+)
--
2.47.0
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] dt-bindings: riscv: add bfloat16 ISA extension description
2024-10-28 7:17 [PATCH 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto
@ 2024-10-28 7:17 ` Inochi Amaoto
2024-10-28 7:17 ` [PATCH 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension Inochi Amaoto
2024-10-28 7:17 ` [PATCH 3/3] riscv: hwprobe: export " Inochi Amaoto
2 siblings, 0 replies; 6+ messages in thread
From: Inochi Amaoto @ 2024-10-28 7:17 UTC (permalink / raw)
To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Clément Léger, Evan Green, Charlie Jenkins,
Andrew Jones, Andy Chiu, Inochi Amaoto, Xiao Wang, Samuel Holland
Cc: linux-doc, linux-riscv, linux-kernel, devicetree
Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 2cf2026cff57..99d8b70fa321 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -277,6 +277,12 @@ properties:
instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
riscv-isa-manual.
+ - const: zfbfmin
+ description:
+ The standard Zfbfmin extension which provides minimal support for
+ 16-bit half-precision brain floating-point instructions, as ratified
+ in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
+
- const: zfh
description:
The standard Zfh extension for 16-bit half-precision binary
@@ -467,6 +473,18 @@ properties:
in commit 6f702a2 ("Vector extensions are now ratified") of
riscv-v-spec.
+ - const: zvfbfmin
+ description:
+ The standard Zvfbfmin extension for minimal support for vectored
+ 16-bit half-precision brain floating-point instructions, as ratified
+ in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
+
+ - const: zvfbfwma
+ description:
+ The standard Zvfbfwma extension for vectored half-precision brain
+ floating-point widening multiply-accumulate instructions, as ratified
+ in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
+
- const: zvfh
description:
The standard Zvfh extension for vectored half-precision
@@ -605,6 +623,33 @@ properties:
then:
contains:
const: zca
+ # Zfbfmin depends on F
+ - if:
+ contains:
+ const: zfbfmin
+ then:
+ contains:
+ const: f
+ # Zvfbfmin depends on V or Zve32f
+ - if:
+ contains:
+ const: zvfbfmin
+ then:
+ oneOf:
+ - contains:
+ const: v
+ - contains:
+ const: zve32f
+ # Zvfbfwma depends on Zfbfmin and Zvfbfmin
+ - if:
+ contains:
+ const: zvfbfwma
+ then:
+ allOf:
+ - contains:
+ const: zfbfmin
+ - contains:
+ const: zvfbfmin
allOf:
# Zcf extension does not exist on rv64
--
2.47.0
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension
2024-10-28 7:17 [PATCH 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto
2024-10-28 7:17 ` [PATCH 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto
@ 2024-10-28 7:17 ` Inochi Amaoto
2024-10-28 7:17 ` [PATCH 3/3] riscv: hwprobe: export " Inochi Amaoto
2 siblings, 0 replies; 6+ messages in thread
From: Inochi Amaoto @ 2024-10-28 7:17 UTC (permalink / raw)
To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Clément Léger, Evan Green, Charlie Jenkins,
Andrew Jones, Andy Chiu, Inochi Amaoto, Xiao Wang, Samuel Holland
Cc: linux-doc, linux-riscv, linux-kernel, devicetree
Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which
were ratified in 4dc23d62 ("Added Chapter title to BF16") of
the riscv-isa-manual.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/include/asm/hwcap.h | 3 +++
arch/riscv/kernel/cpufeature.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 46d9de54179e..97657fb63af6 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -93,6 +93,9 @@
#define RISCV_ISA_EXT_ZCMOP 84
#define RISCV_ISA_EXT_ZAWRS 85
#define RISCV_ISA_EXT_SVVPTC 86
+#define RISCV_ISA_EXT_ZFBFMIN 87
+#define RISCV_ISA_EXT_ZVFBFMIN 88
+#define RISCV_ISA_EXT_ZVFBFWMA 89
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3a8eeaa9310c..1b286f5bc591 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -325,6 +325,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
__RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
+ __RISCV_ISA_EXT_DATA(zfbfmin, RISCV_ISA_EXT_ZFBFMIN),
__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
__RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
@@ -357,6 +358,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
+ __RISCV_ISA_EXT_DATA(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN),
+ __RISCV_ISA_EXT_DATA(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA),
__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
--
2.47.0
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] riscv: hwprobe: export bfloat16 ISA extension
2024-10-28 7:17 [PATCH 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto
2024-10-28 7:17 ` [PATCH 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto
2024-10-28 7:17 ` [PATCH 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension Inochi Amaoto
@ 2024-10-28 7:17 ` Inochi Amaoto
2024-10-30 9:48 ` Clément Léger
2 siblings, 1 reply; 6+ messages in thread
From: Inochi Amaoto @ 2024-10-28 7:17 UTC (permalink / raw)
To: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Clément Léger, Evan Green, Charlie Jenkins,
Andrew Jones, Andy Chiu, Inochi Amaoto, Xiao Wang, Samuel Holland
Cc: linux-doc, linux-riscv, linux-kernel, devicetree
Export Zfbmin, Zvfbfmin, Zvfbfwma ISA extension through hwprobe.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
Documentation/arch/riscv/hwprobe.rst | 12 ++++++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 3 +++
2 files changed, 15 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 85b709257918..8c30dd06f3c0 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -239,6 +239,18 @@ The following keys are defined:
ratified in commit 98918c844281 ("Merge pull request #1217 from
riscv/zawrs") of riscv-isa-manual.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
+ defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+ ("Added Chapter title to BF16").
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
+ defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+ ("Added Chapter title to BF16").
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
+ defined in the RISC-V ISA manual starting from commit 4dc23d6229de
+ ("Added Chapter title to BF16").
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
mistakenly classified as a bitmask rather than a value.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 1e153cda57db..95d00a065b4e 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -72,6 +72,9 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZCF (1ULL << 46)
#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
#define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
+#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 49)
+#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 50)
+#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 51)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
--
2.47.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] riscv: hwprobe: export bfloat16 ISA extension
2024-10-28 7:17 ` [PATCH 3/3] riscv: hwprobe: export " Inochi Amaoto
@ 2024-10-30 9:48 ` Clément Léger
2024-10-31 0:54 ` Inochi Amaoto
0 siblings, 1 reply; 6+ messages in thread
From: Clément Léger @ 2024-10-30 9:48 UTC (permalink / raw)
To: Inochi Amaoto, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Evan Green, Charlie Jenkins, Andrew Jones, Andy Chiu, Xiao Wang,
Samuel Holland
Cc: linux-doc, linux-riscv, linux-kernel, devicetree
On 28/10/2024 08:17, Inochi Amaoto wrote:
> Export Zfbmin, Zvfbfmin, Zvfbfwma ISA extension through hwprobe.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> Documentation/arch/riscv/hwprobe.rst | 12 ++++++++++++
> arch/riscv/include/uapi/asm/hwprobe.h | 3 +++
> 2 files changed, 15 insertions(+)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 85b709257918..8c30dd06f3c0 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -239,6 +239,18 @@ The following keys are defined:
> ratified in commit 98918c844281 ("Merge pull request #1217 from
> riscv/zawrs") of riscv-isa-manual.
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
> + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> + ("Added Chapter title to BF16").
> +
> + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
> + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> + ("Added Chapter title to BF16").
> +
> + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
> + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> + ("Added Chapter title to BF16").
> +
> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
> :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
> mistakenly classified as a bitmask rather than a value.
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 1e153cda57db..95d00a065b4e 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -72,6 +72,9 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46)
> #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
> #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
> +#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 49)
> +#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 50)
> +#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 51)
Hi Inochi,
These should be added as well in sys_hwprobe.c (see hwprobe_isa_ext0()).
Thanks,
Clément
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] riscv: hwprobe: export bfloat16 ISA extension
2024-10-30 9:48 ` Clément Léger
@ 2024-10-31 0:54 ` Inochi Amaoto
0 siblings, 0 replies; 6+ messages in thread
From: Inochi Amaoto @ 2024-10-31 0:54 UTC (permalink / raw)
To: Clément Léger, Inochi Amaoto, Jonathan Corbet,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
Rob Herring, Krzysztof Kozlowski, Evan Green, Charlie Jenkins,
Andrew Jones, Andy Chiu, Xiao Wang, Samuel Holland
Cc: linux-doc, linux-riscv, linux-kernel, devicetree
On Wed, Oct 30, 2024 at 10:48:47AM +0100, Clément Léger wrote:
>
>
> On 28/10/2024 08:17, Inochi Amaoto wrote:
> > Export Zfbmin, Zvfbfmin, Zvfbfwma ISA extension through hwprobe.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > ---
> > Documentation/arch/riscv/hwprobe.rst | 12 ++++++++++++
> > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index 85b709257918..8c30dd06f3c0 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -239,6 +239,18 @@ The following keys are defined:
> > ratified in commit 98918c844281 ("Merge pull request #1217 from
> > riscv/zawrs") of riscv-isa-manual.
> >
> > + * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
> > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> > + ("Added Chapter title to BF16").
> > +
> > + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
> > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> > + ("Added Chapter title to BF16").
> > +
> > + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
> > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de
> > + ("Added Chapter title to BF16").
> > +
> > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
> > :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
> > mistakenly classified as a bitmask rather than a value.
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index 1e153cda57db..95d00a065b4e 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -72,6 +72,9 @@ struct riscv_hwprobe {
> > #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46)
> > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
> > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
> > +#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 49)
> > +#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 50)
> > +#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 51)
>
> Hi Inochi,
>
> These should be added as well in sys_hwprobe.c (see hwprobe_isa_ext0()).
>
> Thanks,
>
> Clément
>
OK, I will add it, thanks for the reminder.
Regards,
Inochi
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^ permalink raw reply [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-28 7:17 [PATCH 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto
2024-10-28 7:17 ` [PATCH 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto
2024-10-28 7:17 ` [PATCH 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension Inochi Amaoto
2024-10-28 7:17 ` [PATCH 3/3] riscv: hwprobe: export " Inochi Amaoto
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