[PATCH v2] RISC-V: Enable cbo.clean/flush in usermode

[PATCH v2] RISC-V: Enable cbo.clean/flush in usermode

[Yunhui Cui]

Enabling cbo.clean and cbo.flush in user mode makes it more
convenient to manage the cache state and achieve better performance.

Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
---
 arch/riscv/kernel/cpufeature.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c0916ed318c2..60d180b98f52 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -30,6 +30,7 @@
 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
 
 static bool any_cpu_has_zicboz;
+static bool any_cpu_has_zicbom;
 
 unsigned long elf_hwcap __read_mostly;
 
@@ -87,6 +88,8 @@ static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,
 		pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
 		return -EINVAL;
 	}
+
+	any_cpu_has_zicbom = true;
 	return 0;
 }
 
@@ -944,6 +947,11 @@ void __init riscv_user_isa_enable(void)
 		current->thread.envcfg |= ENVCFG_CBZE;
 	else if (any_cpu_has_zicboz)
 		pr_warn("Zicboz disabled as it is unavailable on some harts\n");
+
+	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM))
+		current->thread.envcfg |= ENVCFG_CBCFE;
+	else if (any_cpu_has_zicbom)
+		pr_warn("Zicbom disabled as it is unavailable on some harts\n");
 }
 
 #ifdef CONFIG_RISCV_ALTERNATIVE
-- 
2.39.2


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Re: [PATCH v2] RISC-V: Enable cbo.clean/flush in usermode

[Andrew Jones]

On Tue, Dec 24, 2024 at 08:39:46PM +0800, Yunhui Cui wrote:
> Enabling cbo.clean and cbo.flush in user mode makes it more
> convenient to manage the cache state and achieve better performance.
> 
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index c0916ed318c2..60d180b98f52 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -30,6 +30,7 @@
>  #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
>  
>  static bool any_cpu_has_zicboz;
> +static bool any_cpu_has_zicbom;
>  
>  unsigned long elf_hwcap __read_mostly;
>  
> @@ -87,6 +88,8 @@ static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,
>  		pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
>  		return -EINVAL;
>  	}
> +
> +	any_cpu_has_zicbom = true;
>  	return 0;
>  }
>  
> @@ -944,6 +947,11 @@ void __init riscv_user_isa_enable(void)
>  		current->thread.envcfg |= ENVCFG_CBZE;
>  	else if (any_cpu_has_zicboz)
>  		pr_warn("Zicboz disabled as it is unavailable on some harts\n");
> +
> +	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM))
> +		current->thread.envcfg |= ENVCFG_CBCFE;
> +	else if (any_cpu_has_zicbom)
> +		pr_warn("Zicbom disabled as it is unavailable on some harts\n");
>  }
>  
>  #ifdef CONFIG_RISCV_ALTERNATIVE
> -- 
> 2.39.2
>

This looks good, so

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

but, as a separate patch, we should also provide hwprobe support like
zicboz has, i.e. add ZICBOM to the IMA ext0 key and add a key for the
zicbom block size. And then, as another patch, add a test_zicbom()
function to tools/testing/selftests/riscv/hwprobe/cbo.c.

Thanks,
drew

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Re: [External] Re: [PATCH v2] RISC-V: Enable cbo.clean/flush in usermode

[yunhui cui]

Hi drew,

On Tue, Dec 24, 2024 at 10:11 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Tue, Dec 24, 2024 at 08:39:46PM +0800, Yunhui Cui wrote:
> > Enabling cbo.clean and cbo.flush in user mode makes it more
> > convenient to manage the cache state and achieve better performance.
> >
> > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > ---
> >  arch/riscv/kernel/cpufeature.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index c0916ed318c2..60d180b98f52 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -30,6 +30,7 @@
> >  #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
> >
> >  static bool any_cpu_has_zicboz;
> > +static bool any_cpu_has_zicbom;
> >
> >  unsigned long elf_hwcap __read_mostly;
> >
> > @@ -87,6 +88,8 @@ static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,
> >               pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
> >               return -EINVAL;
> >       }
> > +
> > +     any_cpu_has_zicbom = true;
> >       return 0;
> >  }
> >
> > @@ -944,6 +947,11 @@ void __init riscv_user_isa_enable(void)
> >               current->thread.envcfg |= ENVCFG_CBZE;
> >       else if (any_cpu_has_zicboz)
> >               pr_warn("Zicboz disabled as it is unavailable on some harts\n");
> > +
> > +     if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM))
> > +             current->thread.envcfg |= ENVCFG_CBCFE;
> > +     else if (any_cpu_has_zicbom)
> > +             pr_warn("Zicbom disabled as it is unavailable on some harts\n");
> >  }
> >
> >  #ifdef CONFIG_RISCV_ALTERNATIVE
> > --
> > 2.39.2
> >
>
> This looks good, so
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> but, as a separate patch, we should also provide hwprobe support like
> zicboz has, i.e. add ZICBOM to the IMA ext0 key and add a key for the
> zicbom block size. And then, as another patch, add a test_zicbom()
> function to tools/testing/selftests/riscv/hwprobe/cbo.c.
>
> Thanks,
> drew

Thank you for your review. Even though hwprobe doesn't export ZICBOM
currently, user-mode workarounds can still be used.
Alright, I'll send two patches next to support hwprobe's export of
ZICBOM and improve the cbo.c in selftests/.

Thanks,
Yunhui

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