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From: Palmer Dabbelt <palmer@rivosinc.com>
To: linux-riscv@lists.infradead.org
Cc: alex@ghiti.fr, Charlie Jenkins <charlie@rivosinc.com>,
	Mr.Bossman075@gmail.com, Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH v2 2/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x
Date: Wed,  5 Feb 2025 12:40:27 -0800	[thread overview]
Message-ID: <20250205204129.10639-3-palmer@rivosinc.com> (raw)
In-Reply-To: <20250205204129.10639-1-palmer@rivosinc.com>

There were a few of these outside hwprobe, so I figured it was easier to
just clean them up too.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/include/asm/csr.h       | 10 +++++-----
 arch/riscv/include/asm/kasan.h     |  2 +-
 tools/arch/riscv/include/asm/csr.h | 20 ++++++++++----------
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 6fed42e37705..181867da7fe3 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -221,15 +221,15 @@
 
 /* Smstateen bits */
 #define SMSTATEEN0_AIA_IMSIC_SHIFT	58
-#define SMSTATEEN0_AIA_IMSIC		(_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
+#define SMSTATEEN0_AIA_IMSIC		BIT_ULL(SMSTATEEN0_AIA_IMSIC_SHIFT)
 #define SMSTATEEN0_AIA_SHIFT		59
-#define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)
+#define SMSTATEEN0_AIA			BIT_ULL(SMSTATEEN0_AIA_SHIFT)
 #define SMSTATEEN0_AIA_ISEL_SHIFT	60
-#define SMSTATEEN0_AIA_ISEL		(_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT)
+#define SMSTATEEN0_AIA_ISEL		BIT_ULL(SMSTATEEN0_AIA_ISEL_SHIFT)
 #define SMSTATEEN0_HSENVCFG_SHIFT	62
-#define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
+#define SMSTATEEN0_HSENVCFG		BIT_ULL(SMSTATEEN0_HSENVCFG_SHIFT)
 #define SMSTATEEN0_SSTATEEN0_SHIFT	63
-#define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
+#define SMSTATEEN0_SSTATEEN0		BIT_ULL(SMSTATEEN0_SSTATEEN0_SHIFT)
 
 /* mseccfg bits */
 #define MSECCFG_PMM			ENVCFG_PMM
diff --git a/arch/riscv/include/asm/kasan.h b/arch/riscv/include/asm/kasan.h
index e6a0071bdb56..70660f431f8f 100644
--- a/arch/riscv/include/asm/kasan.h
+++ b/arch/riscv/include/asm/kasan.h
@@ -25,7 +25,7 @@
  */
 #define KASAN_SHADOW_SCALE_SHIFT	3
 
-#define KASAN_SHADOW_SIZE	(UL(1) << ((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT))
+#define KASAN_SHADOW_SIZE	BIT_ULL((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)
 /*
  * Depending on the size of the virtual address space, the region may not be
  * aligned on PGDIR_SIZE, so force its alignment to ease its population.
diff --git a/tools/arch/riscv/include/asm/csr.h b/tools/arch/riscv/include/asm/csr.h
index 0dfc09254f99..902d607c282e 100644
--- a/tools/arch/riscv/include/asm/csr.h
+++ b/tools/arch/riscv/include/asm/csr.h
@@ -203,16 +203,16 @@
 #define ENVCFG_FIOM			_AC(0x1, UL)
 
 /* Smstateen bits */
-#define SMSTATEEN0_AIA_IMSIC_SHIFT	58
-#define SMSTATEEN0_AIA_IMSIC		(_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
-#define SMSTATEEN0_AIA_SHIFT		59
-#define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)
-#define SMSTATEEN0_AIA_ISEL_SHIFT	60
-#define SMSTATEEN0_AIA_ISEL		(_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT)
-#define SMSTATEEN0_HSENVCFG_SHIFT	62
-#define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
-#define SMSTATEEN0_SSTATEEN0_SHIFT	63
-#define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
+#define SMSTATEEN0_AIA_IMSIC_SHIFT	BIT_ULL(58)
+#define SMSTATEEN0_AIA_IMSIC		BIT_ULL(SMSTATEEN0_AIA_IMSIC_SHIFT)
+#define SMSTATEEN0_AIA_SHIFT		BIT_ULL(59)
+#define SMSTATEEN0_AIA			BIT_ULL(SMSTATEEN0_AIA_SHIFT)
+#define SMSTATEEN0_AIA_ISEL_SHIFT	BIT_ULL(60)
+#define SMSTATEEN0_AIA_ISEL		BIT_ULL(SMSTATEEN0_AIA_ISEL_SHIFT)
+#define SMSTATEEN0_HSENVCFG_SHIFT	BIT_ULL(62)
+#define SMSTATEEN0_HSENVCFG		BIT_ULL(SMSTATEEN0_HSENVCFG_SHIFT)
+#define SMSTATEEN0_SSTATEEN0_SHIFT	BIT_ULL(63)
+#define SMSTATEEN0_SSTATEEN0		BIT_ULL(SMSTATEEN0_SSTATEEN0_SHIFT)
 
 /* symbolic CSR names: */
 #define CSR_CYCLE		0xc00
-- 
2.45.2


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  parent reply	other threads:[~2025-02-05 23:53 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-05 20:40 [PATCH v2 0/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Palmer Dabbelt
2025-02-05 20:40 ` [PATCH v2 1/2] RISC-V: hwprobe: Use BIT macro to avoid warnings Palmer Dabbelt
2025-02-06  8:58   ` Andreas Schwab
2025-02-05 20:40 ` Palmer Dabbelt [this message]
2025-02-06  6:15   ` [PATCH v2 2/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Tomasz Jeznach

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