* [PATCH] riscv: dts: starfive: fml13v01: enable pcie1
@ 2025-02-07 9:36 Sandie Cao
2025-02-09 12:11 ` Maud Spierings
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Sandie Cao @ 2025-02-07 9:36 UTC (permalink / raw)
To: Conor Dooley, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
linux-kernel, devicetree, Sandie Cao
Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup;
But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup;
redefine pcie1 gpio and enable pcie1 for pcie based Wi-Fi.
Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
---
.../jh7110-deepcomputing-fml13v01.dts | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
index 30b0715196b6..8d9ce8b69a71 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
@@ -11,6 +11,40 @@ / {
compatible = "deepcomputing,fml13v01", "starfive,jh7110";
};
+&pcie1 {
+ perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
+ phys = <&pciephy1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "okay";
+};
+
+&sysgpio {
+ pcie1_pins: pcie1-0 {
+ clkreq-pins {
+ pinmux = <GPIOMUX(29, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-down;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ wake-pins {
+ pinmux = <GPIOMUX(28, GPOUT_HIGH,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+};
+
&usb0 {
dr_mode = "host";
status = "okay";
base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b
--
2.34.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] riscv: dts: starfive: fml13v01: enable pcie1
2025-02-07 9:36 [PATCH] riscv: dts: starfive: fml13v01: enable pcie1 Sandie Cao
@ 2025-02-09 12:11 ` Maud Spierings
2025-02-19 13:43 ` Emil Renner Berthing
2025-02-19 17:39 ` Conor Dooley
2 siblings, 0 replies; 4+ messages in thread
From: Maud Spierings @ 2025-02-09 12:11 UTC (permalink / raw)
To: Sandie Cao, Conor Dooley, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
linux-kernel, devicetree
On 2/7/25 10:36 AM, Sandie Cao wrote:
> Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup;
> But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup;
> redefine pcie1 gpio and enable pcie1 for pcie based Wi-Fi.
>
> Signed-off-by: Sandie Cao<sandie.cao@deepcomputing.io>
> ---
> .../jh7110-deepcomputing-fml13v01.dts | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> index 30b0715196b6..8d9ce8b69a71 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> @@ -11,6 +11,40 @@ / {
> compatible = "deepcomputing,fml13v01", "starfive,jh7110";
> };
>
> +&pcie1 {
> + perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
> + phys = <&pciephy1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_pins>;
> + status = "okay";
> +};
> +
> +&sysgpio {
> + pcie1_pins: pcie1-0 {
> + clkreq-pins {
> + pinmux = <GPIOMUX(29, GPOUT_LOW,
> + GPOEN_DISABLE,
> + GPI_NONE)>;
> + bias-pull-down;
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + wake-pins {
> + pinmux = <GPIOMUX(28, GPOUT_HIGH,
> + GPOEN_DISABLE,
> + GPI_NONE)>;
> + bias-pull-up;
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> &usb0 {
> dr_mode = "host";
> status = "okay";
>
> base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b
Tried this on my device and it works as expected
Tested-by: Maud Spierings <maud_spierings@hotmail.com>
Kind regards,
Maud
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] riscv: dts: starfive: fml13v01: enable pcie1
2025-02-07 9:36 [PATCH] riscv: dts: starfive: fml13v01: enable pcie1 Sandie Cao
2025-02-09 12:11 ` Maud Spierings
@ 2025-02-19 13:43 ` Emil Renner Berthing
2025-02-19 17:39 ` Conor Dooley
2 siblings, 0 replies; 4+ messages in thread
From: Emil Renner Berthing @ 2025-02-19 13:43 UTC (permalink / raw)
To: Sandie Cao, Conor Dooley, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
linux-kernel, devicetree
Sandie Cao wrote:
> Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup;
> But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup;
> redefine pcie1 gpio and enable pcie1 for pcie based Wi-Fi.
>
> Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
Unfortunately I don't yet have a board to test this on, but it looks ok to me.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> ---
> .../jh7110-deepcomputing-fml13v01.dts | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> index 30b0715196b6..8d9ce8b69a71 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> @@ -11,6 +11,40 @@ / {
> compatible = "deepcomputing,fml13v01", "starfive,jh7110";
> };
>
> +&pcie1 {
> + perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
> + phys = <&pciephy1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_pins>;
> + status = "okay";
> +};
> +
> +&sysgpio {
> + pcie1_pins: pcie1-0 {
> + clkreq-pins {
> + pinmux = <GPIOMUX(29, GPOUT_LOW,
> + GPOEN_DISABLE,
> + GPI_NONE)>;
> + bias-pull-down;
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + wake-pins {
> + pinmux = <GPIOMUX(28, GPOUT_HIGH,
> + GPOEN_DISABLE,
> + GPI_NONE)>;
> + bias-pull-up;
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> &usb0 {
> dr_mode = "host";
> status = "okay";
>
> base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b
> --
> 2.34.1
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] riscv: dts: starfive: fml13v01: enable pcie1
2025-02-07 9:36 [PATCH] riscv: dts: starfive: fml13v01: enable pcie1 Sandie Cao
2025-02-09 12:11 ` Maud Spierings
2025-02-19 13:43 ` Emil Renner Berthing
@ 2025-02-19 17:39 ` Conor Dooley
2 siblings, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2025-02-19 17:39 UTC (permalink / raw)
To: linux-riscv, Conor Dooley, Emil Renner Berthing, Rob Herring,
Krzysztof Kozlowski, Sandie Cao
Cc: Conor Dooley, devicetree, linux-kernel, Paul Walmsley,
Palmer Dabbelt, Albert Ou
From: Conor Dooley <conor.dooley@microchip.com>
On Fri, 07 Feb 2025 17:36:18 +0800, Sandie Cao wrote:
> Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup;
> But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup;
> redefine pcie1 gpio and enable pcie1 for pcie based Wi-Fi.
>
>
Applied to riscv-dt-for-next, thanks!
[1/1] riscv: dts: starfive: fml13v01: enable pcie1
https://git.kernel.org/conor/c/57b5369f3668
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2025-02-07 9:36 [PATCH] riscv: dts: starfive: fml13v01: enable pcie1 Sandie Cao
2025-02-09 12:11 ` Maud Spierings
2025-02-19 13:43 ` Emil Renner Berthing
2025-02-19 17:39 ` Conor Dooley
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