From: Conor Dooley <conor@kernel.org>
To: Ben Zong-You Xie <ben717@andestech.com>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
tglx@linutronix.de, daniel.lezcano@linaro.org,
prabhakar.mahadev-lad.rj@bp.renesas.com, tim609@andestech.com
Subject: Re: [PATCH 7/9] riscv: dts: andes: add QiLai SoC device tree
Date: Tue, 8 Apr 2025 17:43:19 +0100 [thread overview]
Message-ID: <20250408-activism-botany-351c2e49b4e9@spud> (raw)
In-Reply-To: <20250407104937.315783-8-ben717@andestech.com>
[-- Attachment #1.1: Type: text/plain, Size: 1338 bytes --]
On Mon, Apr 07, 2025 at 06:49:35PM +0800, Ben Zong-You Xie wrote:
> Introduce the initial device tree support for the Andes QiLai SoC.
>
> For further information, you can refer to [1].
>
> [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
>
> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> ---
> MAINTAINERS | 1 +
> arch/riscv/boot/dts/andes/qilai.dtsi | 194 +++++++++++++++++++++++++++
> 2 files changed, 195 insertions(+)
> create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d1e1b98dfe7b..b974e83c9f10 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20731,6 +20731,7 @@ S: Maintained
> F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
> F: Documentation/devicetree/bindings/riscv/andes.yaml
> F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
> +F: arch/riscv/boot/dts/andes/
New platform, but your maintainers entry contains no git tree. Who are
you expecting to apply patches and send PRs to the soc maintainers for
this platform? Hint: I really hope it is you.
If it is you, please look at the soc platform maintainers documentation
entry:
https://docs.kernel.org/process/maintainer-soc.html
Cheers,
Conor.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2025-04-08 16:45 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-07 10:49 [PATCH 0/9] add Voyager board support Ben Zong-You Xie
2025-04-07 10:49 ` [PATCH 1/9] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
2025-04-07 10:49 ` [PATCH 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Ben Zong-You Xie
2025-04-07 14:13 ` Rob Herring (Arm)
2025-04-07 10:49 ` [PATCH 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Ben Zong-You Xie
2025-04-07 14:14 ` Rob Herring (Arm)
2025-04-07 10:49 ` [PATCH 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Ben Zong-You Xie
2025-04-07 14:17 ` Rob Herring
2025-04-21 12:19 ` Ben Zong-You Xie
2025-04-07 10:49 ` [PATCH 5/9] dt-bindings: timer: add Andes machine timer Ben Zong-You Xie
2025-04-07 14:18 ` Rob Herring
2025-04-07 10:49 ` [PATCH 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache Ben Zong-You Xie
2025-04-07 14:19 ` Rob Herring (Arm)
2025-04-07 10:49 ` [PATCH 7/9] riscv: dts: andes: add QiLai SoC device tree Ben Zong-You Xie
2025-04-07 14:30 ` Krzysztof Kozlowski
2025-04-08 16:43 ` Conor Dooley [this message]
2025-04-07 10:49 ` [PATCH 8/9] riscv: dts: andes: add Voyager board " Ben Zong-You Xie
2025-04-07 14:31 ` Krzysztof Kozlowski
2025-04-07 10:49 ` [PATCH 9/9] riscv: defconfig: enable Andes SoC Ben Zong-You Xie
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250408-activism-botany-351c2e49b4e9@spud \
--to=conor@kernel.org \
--cc=alex@ghiti.fr \
--cc=aou@eecs.berkeley.edu \
--cc=ben717@andestech.com \
--cc=conor+dt@kernel.org \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=robh@kernel.org \
--cc=tglx@linutronix.de \
--cc=tim609@andestech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox