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From: Inochi Amaoto <inochiama@gmail.com>
To: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@gmail.com>,
	Richard Cochran <richardcochran@gmail.com>,
	Longbin Li <looong.bin@gmail.com>
Cc: Han Gao <rabenda.cn@gmail.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	sophgo@lists.linux.dev, linux-kernel@vger.kernel.org,
	netdev@vger.kernel.org, Yixun Lan <dlan@gentoo.org>
Subject: [PATCH 02/11] riscv: dts: sophgo: sg2044: Add clock controller device
Date: Mon,  9 Jun 2025 07:28:26 +0800	[thread overview]
Message-ID: <20250608232836.784737-3-inochiama@gmail.com> (raw)
In-Reply-To: <20250608232836.784737-1-inochiama@gmail.com>

Add clock controller and pll clock node for sg2044.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
 arch/riscv/boot/dts/sophgo/sg2044.dtsi | 34 ++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index a0c13d8d26af..d21a59948186 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
  */
 
+#include <dt-bindings/clock/sophgo,sg2044-pll.h>
+#include <dt-bindings/clock/sophgo,sg2044-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 #include "sg2044-cpus.dtsi"
@@ -32,6 +34,9 @@ uart0: serial@7030000000 {
 			compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
 			reg = <0x70 0x30000000 0x0 0x1000>;
 			clock-frequency = <500000000>;
+			clocks = <&clk CLK_GATE_UART_500M>,
+				 <&clk CLK_GATE_APB_UART>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupt-parent = <&intc>;
 			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
@@ -44,6 +49,9 @@ uart1: serial@7030001000 {
 			compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
 			reg = <0x70 0x30001000 0x0 0x1000>;
 			clock-frequency = <500000000>;
+			clocks = <&clk CLK_GATE_UART_500M>,
+				 <&clk CLK_GATE_APB_UART>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupt-parent = <&intc>;
 			interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
@@ -56,6 +64,9 @@ uart2: serial@7030002000 {
 			compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
 			reg = <0x70 0x30002000 0x0 0x1000>;
 			clock-frequency = <500000000>;
+			clocks = <&clk CLK_GATE_UART_500M>,
+				 <&clk CLK_GATE_APB_UART>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupt-parent = <&intc>;
 			interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
@@ -68,6 +79,9 @@ uart3: serial@7030003000 {
 			compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
 			reg = <0x70 0x30003000 0x0 0x1000>;
 			clock-frequency = <500000000>;
+			clocks = <&clk CLK_GATE_UART_500M>,
+				 <&clk CLK_GATE_APB_UART>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupt-parent = <&intc>;
 			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
@@ -83,6 +97,26 @@ syscon: syscon@7050000000 {
 			clocks = <&osc>;
 		};
 
+		clk: clock-controller@7050002000 {
+			compatible = "sophgo,sg2044-clk";
+			reg = <0x70 0x50002000 0x0 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
+				 <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
+				 <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
+				 <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
+				 <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
+				 <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
+				 <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
+				 <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
+				 <&syscon CLK_MPLL5>;
+			clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
+				      "dpll1", "dpll2", "dpll3", "dpll4",
+				      "dpll5", "dpll6", "dpll7", "mpll0",
+				      "mpll1", "mpll2", "mpll3", "mpll4",
+				      "mpll5";
+		};
+
 		rst: reset-controller@7050003000 {
 			compatible = "sophgo,sg2044-reset",
 				     "sophgo,sg2042-reset";
-- 
2.49.0


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  parent reply	other threads:[~2025-06-08 23:29 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
2025-06-08 23:28 ` [PATCH 01/11] riscv: dts: sophgo: sg2044: Add system controller device Inochi Amaoto
2025-06-08 23:28 ` Inochi Amaoto [this message]
2025-06-08 23:28 ` [PATCH 03/11] riscv: dts: sophgo: sg2044: Add GPIO device Inochi Amaoto
2025-06-08 23:28 ` [PATCH 04/11] riscv: dts: sophgo: sg2044: Add I2C device Inochi Amaoto
2025-06-08 23:28 ` [PATCH 05/11] riscv: dts: sophgo: sg2044: add DMA controller device Inochi Amaoto
2025-06-08 23:28 ` [PATCH 06/11] riscv: dts: sophgo: sg2044: Add MMC " Inochi Amaoto
2025-06-08 23:28 ` [PATCH 07/11] riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device Inochi Amaoto
2025-06-08 23:28 ` [PATCH 08/11] riscv: dts: sophgo: sg2044: Add ethernet control device Inochi Amaoto
2025-06-08 23:28 ` [PATCH 09/11] riscv: dts: sophgo: sg2044: Add pinctrl device Inochi Amaoto
2025-06-08 23:28 ` [PATCH 10/11] riscv: dts: sophgo: add SG2044 SPI NOR controller driver Inochi Amaoto
2025-06-08 23:28 ` [PATCH 11/11] riscv: dts: sophgo: add pwm controller for SG2044 Inochi Amaoto
2025-06-11  9:53   ` Chen Wang
2025-06-11 10:17     ` Inochi Amaoto
2025-06-17  5:07 ` [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto

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