[PATCH] RISC-V: KVM: Write hgatp register with valid mode bits

[PATCH] RISC-V: KVM: Write hgatp register with valid mode bits

[fangyu.yu]

From: Fangyu Yu <fangyu.yu@linux.alibaba.com>

According to the RISC-V Privileged Architecture Spec, when MODE=Bare
is selected,software must write zero to the remaining fields of hgatp.

We have detected the valid mode supported by the HW before, So using a
valid mode to detect how many vmid bits are supported.

Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
 arch/riscv/kvm/vmid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c
index 3b426c800480..d176a5c2f9a4 100644
--- a/arch/riscv/kvm/vmid.c
+++ b/arch/riscv/kvm/vmid.c
@@ -28,7 +28,7 @@ void __init kvm_riscv_gstage_vmid_detect(void)
 
 	/* Figure-out number of VMID bits in HW */
 	old = csr_read(CSR_HGATP);
-	csr_write(CSR_HGATP, old | HGATP_VMID);
+	csr_write(CSR_HGATP, (kvm_riscv_gstage_mode() << HGATP_MODE_SHIFT) | HGATP_VMID);
 	vmid_bits = csr_read(CSR_HGATP);
 	vmid_bits = (vmid_bits & HGATP_VMID) >> HGATP_VMID_SHIFT;
 	vmid_bits = fls_long(vmid_bits);
-- 
2.49.0


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Re: [PATCH] RISC-V: KVM: Write hgatp register with valid mode bits

[kernel test robot]

Hi,

kernel test robot noticed the following build warnings:

[auto build test WARNING on kvm/queue]
[also build test WARNING on kvm/next mst-vhost/linux-next linus/master v6.17-rc1 next-20250815]
[cannot apply to kvm/linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/fangyu-yu-linux-alibaba-com/RISC-V-KVM-Write-hgatp-register-with-valid-mode-bits/20250816-153513
base:   https://git.kernel.org/pub/scm/virt/kvm/kvm.git queue
patch link:    https://lore.kernel.org/r/20250816073234.77646-1-fangyu.yu%40linux.alibaba.com
patch subject: [PATCH] RISC-V: KVM: Write hgatp register with valid mode bits
config: riscv-allyesconfig (https://download.01.org/0day-ci/archive/20250817/202508171655.76Ifmphq-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250817/202508171655.76Ifmphq-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508171655.76Ifmphq-lkp@intel.com/

All warnings (new ones prefixed by >>):

   arch/riscv/kvm/vmid.c:31:24: error: call to undeclared function 'kvm_riscv_gstage_mode'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           csr_write(CSR_HGATP, (kvm_riscv_gstage_mode() << HGATP_MODE_SHIFT) | HGATP_VMID);
                                 ^
>> arch/riscv/kvm/vmid.c:31:48: warning: shift count >= width of type [-Wshift-count-overflow]
           csr_write(CSR_HGATP, (kvm_riscv_gstage_mode() << HGATP_MODE_SHIFT) | HGATP_VMID);
                                                         ^  ~~~~~~~~~~~~~~~~
   arch/riscv/include/asm/csr.h:538:38: note: expanded from macro 'csr_write'
           unsigned long __v = (unsigned long)(val);               \
                                               ^~~
   1 warning and 1 error generated.


vim +31 arch/riscv/kvm/vmid.c

    24	
    25	void __init kvm_riscv_gstage_vmid_detect(void)
    26	{
    27		unsigned long old;
    28	
    29		/* Figure-out number of VMID bits in HW */
    30		old = csr_read(CSR_HGATP);
  > 31		csr_write(CSR_HGATP, (kvm_riscv_gstage_mode() << HGATP_MODE_SHIFT) | HGATP_VMID);
    32		vmid_bits = csr_read(CSR_HGATP);
    33		vmid_bits = (vmid_bits & HGATP_VMID) >> HGATP_VMID_SHIFT;
    34		vmid_bits = fls_long(vmid_bits);
    35		csr_write(CSR_HGATP, old);
    36	
    37		/* We polluted local TLB so flush all guest TLB */
    38		kvm_riscv_local_hfence_gvma_all();
    39	
    40		/* We don't use VMID bits if they are not sufficient */
    41		if ((1UL << vmid_bits) < num_possible_cpus())
    42			vmid_bits = 0;
    43	}
    44	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

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Re: [PATCH] RISC-V: KVM: Write hgatp register with valid mode bits

[kernel test robot]

Hi,

kernel test robot noticed the following build errors:

[auto build test ERROR on kvm/queue]
[also build test ERROR on kvm/next mst-vhost/linux-next linus/master v6.17-rc1 next-20250815]
[cannot apply to kvm/linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/fangyu-yu-linux-alibaba-com/RISC-V-KVM-Write-hgatp-register-with-valid-mode-bits/20250816-153513
base:   https://git.kernel.org/pub/scm/virt/kvm/kvm.git queue
patch link:    https://lore.kernel.org/r/20250816073234.77646-1-fangyu.yu%40linux.alibaba.com
patch subject: [PATCH] RISC-V: KVM: Write hgatp register with valid mode bits
config: riscv-allyesconfig (https://download.01.org/0day-ci/archive/20250818/202508180228.aJykn9j0-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250818/202508180228.aJykn9j0-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508180228.aJykn9j0-lkp@intel.com/

All errors (new ones prefixed by >>):

>> arch/riscv/kvm/vmid.c:31:24: error: call to undeclared function 'kvm_riscv_gstage_mode'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           csr_write(CSR_HGATP, (kvm_riscv_gstage_mode() << HGATP_MODE_SHIFT) | HGATP_VMID);
                                 ^
   arch/riscv/kvm/vmid.c:31:48: warning: shift count >= width of type [-Wshift-count-overflow]
           csr_write(CSR_HGATP, (kvm_riscv_gstage_mode() << HGATP_MODE_SHIFT) | HGATP_VMID);
                                                         ^  ~~~~~~~~~~~~~~~~
   arch/riscv/include/asm/csr.h:538:38: note: expanded from macro 'csr_write'
           unsigned long __v = (unsigned long)(val);               \
                                               ^~~
   1 warning and 1 error generated.


vim +/kvm_riscv_gstage_mode +31 arch/riscv/kvm/vmid.c

    24	
    25	void __init kvm_riscv_gstage_vmid_detect(void)
    26	{
    27		unsigned long old;
    28	
    29		/* Figure-out number of VMID bits in HW */
    30		old = csr_read(CSR_HGATP);
  > 31		csr_write(CSR_HGATP, (kvm_riscv_gstage_mode() << HGATP_MODE_SHIFT) | HGATP_VMID);
    32		vmid_bits = csr_read(CSR_HGATP);
    33		vmid_bits = (vmid_bits & HGATP_VMID) >> HGATP_VMID_SHIFT;
    34		vmid_bits = fls_long(vmid_bits);
    35		csr_write(CSR_HGATP, old);
    36	
    37		/* We polluted local TLB so flush all guest TLB */
    38		kvm_riscv_local_hfence_gvma_all();
    39	
    40		/* We don't use VMID bits if they are not sufficient */
    41		if ((1UL << vmid_bits) < num_possible_cpus())
    42			vmid_bits = 0;
    43	}
    44	

-- 
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https://github.com/intel/lkp-tests/wiki

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