* [PATCH] cache: sifive_ccache: Optimize cache flushes
@ 2025-09-09 22:41 Samuel Holland
2025-09-11 18:24 ` Conor Dooley
0 siblings, 1 reply; 2+ messages in thread
From: Samuel Holland @ 2025-09-09 22:41 UTC (permalink / raw)
To: Conor Dooley, Paul Walmsley
Cc: linmin, Pinkesh Vaghela, linux-riscv, linux-kernel,
Samuel Holland
Fence instructions are required only at the beginning and the end of
a flush operation, not separately for each cache line being flushed.
Speed up cache flushes by about 15% by removing the extra fences.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
drivers/cache/sifive_ccache.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c
index e1a283805ea7f..a86800b123b9e 100644
--- a/drivers/cache/sifive_ccache.c
+++ b/drivers/cache/sifive_ccache.c
@@ -151,16 +151,16 @@ static void ccache_flush_range(phys_addr_t start, size_t len)
if (!len)
return;
- mb();
+ mb(); /* complete earlier memory accesses before the cache flush */
for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;
line += SIFIVE_CCACHE_LINE_SIZE) {
#ifdef CONFIG_32BIT
- writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
+ writel_relaxed(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
#else
- writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
+ writeq_relaxed(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
#endif
- mb();
}
+ mb(); /* issue later memory accesses after the cache flush */
}
static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = {
--
2.47.2
base-commit: 9dd1835ecda5b96ac88c166f4a87386f3e727bd9
branch: up/ccache-flush-opt
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^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] cache: sifive_ccache: Optimize cache flushes
2025-09-09 22:41 [PATCH] cache: sifive_ccache: Optimize cache flushes Samuel Holland
@ 2025-09-11 18:24 ` Conor Dooley
0 siblings, 0 replies; 2+ messages in thread
From: Conor Dooley @ 2025-09-11 18:24 UTC (permalink / raw)
To: Conor Dooley, Paul Walmsley, Samuel Holland
Cc: Conor Dooley, linmin, Pinkesh Vaghela, linux-riscv, linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
On Tue, 09 Sep 2025 15:41:27 -0700, Samuel Holland wrote:
> Fence instructions are required only at the beginning and the end of
> a flush operation, not separately for each cache line being flushed.
> Speed up cache flushes by about 15% by removing the extra fences.
>
>
Applied to riscv-cache-for-next, thanks!
[1/1] cache: sifive_ccache: Optimize cache flushes
https://git.kernel.org/conor/c/941327ca5ddd
Thanks,
Conor.
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