From: Andrew Jones <ajones@ventanamicro.com>
To: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
alexghiti@rivosinc.com, shuah@kernel.org,
samuel.holland@sifive.com, evan@rivosinc.com,
cleger@rivosinc.com, zihongyao@outlook.com,
zhangyin2018@iscas.ac.cn, "Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Jesse Taube" <jesse@rivosinc.com>,
"Inochi Amaoto" <inochiama@gmail.com>,
"Aleksa Paunovic" <aleksa.paunovic@htecgroup.com>,
"Thomas Weißschuh" <thomas.weissschuh@linutronix.de>,
"Yunhui Cui" <cuiyunhui@bytedance.com>,
"Nam Cao" <namcao@linutronix.de>
Subject: Re: [PATCH v2 2/4] riscv: hwprobe: Report Zicbop presence and block size
Date: Thu, 9 Oct 2025 12:08:52 -0500 [thread overview]
Message-ID: <20251009-643d7302be8ec611ea622aff@orel> (raw)
In-Reply-To: <20251009134318.23040-3-zihong.plct@isrc.iscas.ac.cn>
On Thu, Oct 09, 2025 at 09:41:52PM +0800, Yao Zihong wrote:
> Plumb Zicbop into hwprobe. Semantics mirror Zicbom/Zicboz to keep
> userspace expectations aligned.
>
> Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
> ---
> arch/riscv/kernel/sys_hwprobe.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 000f4451a9d8..7a6ae1327504 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -113,6 +113,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> EXT_KEY(ZCB);
> EXT_KEY(ZCMOP);
> EXT_KEY(ZICBOM);
> + EXT_KEY(ZICBOP);
> EXT_KEY(ZICBOZ);
> EXT_KEY(ZICNTR);
> EXT_KEY(ZICOND);
> @@ -293,6 +294,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
> pair->value = riscv_cbom_block_size;
> break;
> + case RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE:
> + pair->value = 0;
> + if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOP))
> + pair->value = riscv_cbop_block_size;
> + break;
> case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
> pair->value = user_max_virt_addr();
> break;
> --
> 2.47.2
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
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next prev parent reply other threads:[~2025-10-09 17:09 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-09 13:41 [PATCH v2 0/4] riscv: hwprobe: Add Zicbop support Yao Zihong
2025-10-09 13:41 ` [PATCH v2 1/4] uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key Yao Zihong
2025-10-09 17:08 ` Andrew Jones
2025-10-09 13:41 ` [PATCH v2 2/4] riscv: hwprobe: Report Zicbop presence and block size Yao Zihong
2025-10-09 17:08 ` Andrew Jones [this message]
2025-10-09 13:41 ` [PATCH v2 3/4] docs: riscv: Document hwprobe for Zicbop Yao Zihong
2025-10-09 16:46 ` Andrew Jones
2025-10-09 13:41 ` [PATCH v2 4/4] selftests/riscv: Add Zicbop prefetch test Yao Zihong
2025-10-09 17:06 ` Andrew Jones
2025-10-13 16:16 ` Yao Zihong
2025-10-13 17:41 ` Andrew Jones
2025-10-09 17:09 ` [PATCH v2 0/4] riscv: hwprobe: Add Zicbop support Andrew Jones
2025-10-13 16:15 ` Yao Zihong
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