From: Andrew Jones <ajones@ventanamicro.com>
To: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
alexghiti@rivosinc.com, shuah@kernel.org,
samuel.holland@sifive.com, evan@rivosinc.com,
cleger@rivosinc.com, zihongyao@outlook.com,
zhangyin2018@iscas.ac.cn, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Charlie Jenkins <charlie@rivosinc.com>,
Cyan Yang <cyan.yang@sifive.com>,
Yunhui Cui <cuiyunhui@bytedance.com>,
Aleksa Paunovic <aleksa.paunovic@htecgroup.com>,
Jesse Taube <jesse@rivosinc.com>,
Inochi Amaoto <inochiama@gmail.com>
Subject: Re: [PATCH v2 1/4] uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key
Date: Thu, 9 Oct 2025 12:08:42 -0500 [thread overview]
Message-ID: <20251009-368359384e19820a18cea601@orel> (raw)
In-Reply-To: <20251009134318.23040-2-zihong.plct@isrc.iscas.ac.cn>
On Thu, Oct 09, 2025 at 09:41:51PM +0800, Yao Zihong wrote:
> Introduce RISCV_HWPROBE_EXT_ZICBOP to report presence of the Zicbop
> extension through hwprobe, and add RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE
> to expose the block size (in bytes) when Zicbop is supported.
>
> Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
> ---
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 948d2b34e94e..2f278c395af9 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -8,7 +8,7 @@
>
> #include <uapi/asm/hwprobe.h>
>
> -#define RISCV_HWPROBE_MAX_KEY 14
> +#define RISCV_HWPROBE_MAX_KEY 15
>
> static inline bool riscv_hwprobe_key_is_valid(__s64 key)
> {
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 5d30a4fae37a..9cc508be54c5 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -82,6 +82,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZAAMO (1ULL << 56)
> #define RISCV_HWPROBE_EXT_ZALRSC (1ULL << 57)
> #define RISCV_HWPROBE_EXT_ZABHA (1ULL << 58)
> +#define RISCV_HWPROBE_EXT_ZICBOP (1ULL << 59)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> @@ -107,6 +108,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12
> #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13
> #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0 14
> +#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE 15
> /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>
> /* Flags */
> --
> 2.47.2
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
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next prev parent reply other threads:[~2025-10-09 17:08 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-09 13:41 [PATCH v2 0/4] riscv: hwprobe: Add Zicbop support Yao Zihong
2025-10-09 13:41 ` [PATCH v2 1/4] uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key Yao Zihong
2025-10-09 17:08 ` Andrew Jones [this message]
2025-10-09 13:41 ` [PATCH v2 2/4] riscv: hwprobe: Report Zicbop presence and block size Yao Zihong
2025-10-09 17:08 ` Andrew Jones
2025-10-09 13:41 ` [PATCH v2 3/4] docs: riscv: Document hwprobe for Zicbop Yao Zihong
2025-10-09 16:46 ` Andrew Jones
2025-10-09 13:41 ` [PATCH v2 4/4] selftests/riscv: Add Zicbop prefetch test Yao Zihong
2025-10-09 17:06 ` Andrew Jones
2025-10-13 16:16 ` Yao Zihong
2025-10-13 17:41 ` Andrew Jones
2025-10-09 17:09 ` [PATCH v2 0/4] riscv: hwprobe: Add Zicbop support Andrew Jones
2025-10-13 16:15 ` Yao Zihong
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