[PATCH v2 0/4] riscv: hwprobe: Add Zicbop support

[PATCH v2 0/4] riscv: hwprobe: Add Zicbop support

[Yao Zihong]

Changes since v1:
------------------
- Bump RISCV_HWPROBE_MAX_KEY (modified 1/4).
- Add documentation for the Zicbop hwprobe bit/key (new 3/4).
- Add a selftest(prefetch.c) for Zicbop (new 4/4).

Add UAPI and kernel plumbing to expose the Zicbop extension presence
and its block size through hwprobe. The interface mirrors
Zicbom/Zicboz. This allows userspace to safely discover and optimize
for Zicbop when available.

Background: Zicbop is mandated by the RVA22U64 profile. Downstream may
combine the presence bit with ZICBOP_BLOCK_SIZE to make profile-level
policy decisions or enable Zicbop-specific optimizations.

Yao Zihong (4):
  uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key
  riscv: hwprobe: Report Zicbop presence and block size
  docs: riscv: Document hwprobe for Zicbop
  selftests/riscv: Add Zicbop prefetch test

 Documentation/arch/riscv/hwprobe.rst          |   8 +-
 arch/riscv/include/asm/hwprobe.h              |   2 +-
 arch/riscv/include/uapi/asm/hwprobe.h         |   2 +
 arch/riscv/kernel/sys_hwprobe.c               |   6 +
 .../testing/selftests/riscv/hwprobe/Makefile  |   5 +-
 .../selftests/riscv/hwprobe/prefetch.c        | 236 ++++++++++++++++++
 6 files changed, 256 insertions(+), 3 deletions(-)
 create mode 100644 tools/testing/selftests/riscv/hwprobe/prefetch.c

-- 
2.47.2


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[PATCH v2 1/4] uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key

[Yao Zihong]

Introduce RISCV_HWPROBE_EXT_ZICBOP to report presence of the Zicbop
extension through hwprobe, and add RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE
to expose the block size (in bytes) when Zicbop is supported.

Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
---
 arch/riscv/include/asm/hwprobe.h      | 2 +-
 arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 948d2b34e94e..2f278c395af9 100644
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -8,7 +8,7 @@
 
 #include <uapi/asm/hwprobe.h>
 
-#define RISCV_HWPROBE_MAX_KEY 14
+#define RISCV_HWPROBE_MAX_KEY 15
 
 static inline bool riscv_hwprobe_key_is_valid(__s64 key)
 {
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 5d30a4fae37a..9cc508be54c5 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -82,6 +82,7 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZAAMO		(1ULL << 56)
 #define		RISCV_HWPROBE_EXT_ZALRSC	(1ULL << 57)
 #define		RISCV_HWPROBE_EXT_ZABHA		(1ULL << 58)
+#define		RISCV_HWPROBE_EXT_ZICBOP	(1ULL << 59)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
@@ -107,6 +108,7 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE	12
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0	13
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0	14
+#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE	15
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */
-- 
2.47.2


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Re: [PATCH v2 1/4] uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key

[Andrew Jones]

On Thu, Oct 09, 2025 at 09:41:51PM +0800, Yao Zihong wrote:
> Introduce RISCV_HWPROBE_EXT_ZICBOP to report presence of the Zicbop
> extension through hwprobe, and add RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE
> to expose the block size (in bytes) when Zicbop is supported.
> 
> Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
> ---
>  arch/riscv/include/asm/hwprobe.h      | 2 +-
>  arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 948d2b34e94e..2f278c395af9 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -8,7 +8,7 @@
>  
>  #include <uapi/asm/hwprobe.h>
>  
> -#define RISCV_HWPROBE_MAX_KEY 14
> +#define RISCV_HWPROBE_MAX_KEY 15
>  
>  static inline bool riscv_hwprobe_key_is_valid(__s64 key)
>  {
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 5d30a4fae37a..9cc508be54c5 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -82,6 +82,7 @@ struct riscv_hwprobe {
>  #define		RISCV_HWPROBE_EXT_ZAAMO		(1ULL << 56)
>  #define		RISCV_HWPROBE_EXT_ZALRSC	(1ULL << 57)
>  #define		RISCV_HWPROBE_EXT_ZABHA		(1ULL << 58)
> +#define		RISCV_HWPROBE_EXT_ZICBOP	(1ULL << 59)
>  #define RISCV_HWPROBE_KEY_CPUPERF_0	5
>  #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
>  #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
> @@ -107,6 +108,7 @@ struct riscv_hwprobe {
>  #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE	12
>  #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0	13
>  #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0	14
> +#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE	15
>  /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>  
>  /* Flags */
> -- 
> 2.47.2
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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[PATCH v2 2/4] riscv: hwprobe: Report Zicbop presence and block size

[Yao Zihong]

Plumb Zicbop into hwprobe. Semantics mirror Zicbom/Zicboz to keep
userspace expectations aligned.

Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
---
 arch/riscv/kernel/sys_hwprobe.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 000f4451a9d8..7a6ae1327504 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -113,6 +113,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(ZCB);
 		EXT_KEY(ZCMOP);
 		EXT_KEY(ZICBOM);
+		EXT_KEY(ZICBOP);
 		EXT_KEY(ZICBOZ);
 		EXT_KEY(ZICNTR);
 		EXT_KEY(ZICOND);
@@ -293,6 +294,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
 		if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
 			pair->value = riscv_cbom_block_size;
 		break;
+	case RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE:
+		pair->value = 0;
+		if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOP))
+			pair->value = riscv_cbop_block_size;
+		break;
 	case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
 		pair->value = user_max_virt_addr();
 		break;
-- 
2.47.2


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Re: [PATCH v2 2/4] riscv: hwprobe: Report Zicbop presence and block size

[Andrew Jones]

On Thu, Oct 09, 2025 at 09:41:52PM +0800, Yao Zihong wrote:
> Plumb Zicbop into hwprobe. Semantics mirror Zicbom/Zicboz to keep
> userspace expectations aligned.
> 
> Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
> ---
>  arch/riscv/kernel/sys_hwprobe.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 000f4451a9d8..7a6ae1327504 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -113,6 +113,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
>  		EXT_KEY(ZCB);
>  		EXT_KEY(ZCMOP);
>  		EXT_KEY(ZICBOM);
> +		EXT_KEY(ZICBOP);
>  		EXT_KEY(ZICBOZ);
>  		EXT_KEY(ZICNTR);
>  		EXT_KEY(ZICOND);
> @@ -293,6 +294,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
>  		if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
>  			pair->value = riscv_cbom_block_size;
>  		break;
> +	case RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE:
> +		pair->value = 0;
> +		if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOP))
> +			pair->value = riscv_cbop_block_size;
> +		break;
>  	case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
>  		pair->value = user_max_virt_addr();
>  		break;
> -- 
> 2.47.2
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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[PATCH v2 3/4] docs: riscv: Document hwprobe for Zicbop

[Yao Zihong]

Update hwprobe.rst to include documentation of the new
:c:macro:`RISCV_HWPROBE_EXT_ZICBOP` and
:c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`, following the same
style as the Zicbom and Zicboz entries.

The extension bit records support for the Zicbop extension, and
the block size key reports the block size in bytes.

Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
---
 Documentation/arch/riscv/hwprobe.rst | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 2f449c9b15bd..3b9c9d7e1409 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -275,6 +275,9 @@ The following keys are defined:
        ratified in commit 49f49c842ff9 ("Update to Rafified state") of
        riscv-zabha.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as
+       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to
      :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
      mistakenly classified as a bitmask rather than a value.
@@ -369,4 +372,7 @@ The following keys are defined:
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
         vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
-	Instruction Extensions Specification.
\ No newline at end of file
+	Instruction Extensions Specification.
+
+* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
+  represents the size of the Zicbop block in bytes.
\ No newline at end of file
-- 
2.47.2


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Re: [PATCH v2 3/4] docs: riscv: Document hwprobe for Zicbop

[Andrew Jones]

On Thu, Oct 09, 2025 at 09:41:53PM +0800, Yao Zihong wrote:
> Update hwprobe.rst to include documentation of the new
> :c:macro:`RISCV_HWPROBE_EXT_ZICBOP` and
> :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`, following the same
> style as the Zicbom and Zicboz entries.
> 
> The extension bit records support for the Zicbop extension, and
> the block size key reports the block size in bytes.
> 
> Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
> ---
>  Documentation/arch/riscv/hwprobe.rst | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 2f449c9b15bd..3b9c9d7e1409 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -275,6 +275,9 @@ The following keys are defined:
>         ratified in commit 49f49c842ff9 ("Update to Rafified state") of
>         riscv-zabha.
>  
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as
> +       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
> +
>  * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to
>       :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
>       mistakenly classified as a bitmask rather than a value.
> @@ -369,4 +372,7 @@ The following keys are defined:
>  
>      * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
>          vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
> -	Instruction Extensions Specification.
> \ No newline at end of file
> +	Instruction Extensions Specification.
> +
> +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
> +  represents the size of the Zicbop block in bytes.
> \ No newline at end of file

Please ensure this file has a newline so the last line doesn't have
to change every time we add new keys.

Thanks,
drew

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[PATCH v2 4/4] selftests/riscv: Add Zicbop prefetch test

[Yao Zihong]

Add a new selftest under hwprobe/ to verify Zicbop extension behavior.

The test checks:
- That hwprobe correctly reports Zicbop presence and block size.
- That prefetch instructions execute without exception on valid and NULL
  addresses when Zicbop is present.
- That prefetch.{i,r,w} do not trigger SIGILL even when Zicbop is absent,
  since Zicbop instructions are defined as hints.

The test is based on cbo.c but adapted for Zicbop prefetch instructions.

Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
---
 .../testing/selftests/riscv/hwprobe/Makefile  |   5 +-
 .../selftests/riscv/hwprobe/prefetch.c        | 236 ++++++++++++++++++
 2 files changed, 240 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/riscv/hwprobe/prefetch.c

diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing/selftests/riscv/hwprobe/Makefile
index cec81610a5f2..3c8b8ba7629c 100644
--- a/tools/testing/selftests/riscv/hwprobe/Makefile
+++ b/tools/testing/selftests/riscv/hwprobe/Makefile
@@ -4,7 +4,7 @@
 
 CFLAGS += -I$(top_srcdir)/tools/include
 
-TEST_GEN_PROGS := hwprobe cbo which-cpus
+TEST_GEN_PROGS := hwprobe cbo which-cpus prefetch
 
 include ../../lib.mk
 
@@ -16,3 +16,6 @@ $(OUTPUT)/cbo: cbo.c sys_hwprobe.S
 
 $(OUTPUT)/which-cpus: which-cpus.c sys_hwprobe.S
 	$(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^
+
+$(OUTPUT)/prefetch: prefetch.c sys_hwprobe.S
+	$(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^
diff --git a/tools/testing/selftests/riscv/hwprobe/prefetch.c b/tools/testing/selftests/riscv/hwprobe/prefetch.c
new file mode 100644
index 000000000000..d9ea048325fb
--- /dev/null
+++ b/tools/testing/selftests/riscv/hwprobe/prefetch.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023 Ventana Micro Systems Inc.
+ * Copyright (c) 2025 PLCT Lab, ISCAS
+ *
+ * Based on tools/testing/selftests/riscv/hwprobe/cbo.c with modifications
+ * for Zicbop prefetch testing.
+ *
+ * Run with 'taskset -c <cpu-list> prefetch' to only execute hwprobe on a
+ * subset of cpus, as well as only executing the tests on those cpus.
+ */
+#define _GNU_SOURCE
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <sched.h>
+#include <signal.h>
+#include <assert.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <asm/ucontext.h>
+
+#include "hwprobe.h"
+#include "../../kselftest.h"
+
+#define MK_PREFETCH(fn) \
+	le32_bswap(0 << 25 | (uint32_t)(fn) << 20 | 10 << 15 | 6 << 12 | 0 << 7 | 19)
+
+static char mem[4096] __aligned(4096) = { [0 ... 4095] = 0xa5 };
+
+static bool illegal;
+
+static void sigill_handler(int sig, siginfo_t *info, void *context)
+{
+	unsigned long *regs = (unsigned long *)&((ucontext_t *)context)->uc_mcontext;
+	uint32_t insn = *(uint32_t *)regs[0];
+
+	assert(insn == MK_PREFETCH(regs[11]));
+
+	illegal = true;
+	regs[0] += 4;
+}
+
+#define prefetch_insn(base, fn)							\
+({										\
+	asm volatile(								\
+	"mv	a0, %0\n"							\
+	"li	a1, %1\n"							\
+	".4byte	%2\n"								\
+	: : "r" (base), "i" (fn), "i" (MK_PREFETCH(fn)) : "a0", "a1", "memory");\
+})
+
+static void prefetch_i(char *base) { prefetch_insn(base, 0); }
+
+static void prefetch_r(char *base) { prefetch_insn(base, 1); }
+
+static void prefetch_w(char *base) { prefetch_insn(base, 3); }
+
+static bool is_power_of_2(__u64 n)
+{
+	return n != 0 && (n & (n - 1)) == 0;
+}
+
+static void test_no_zicbop(void *arg)
+{
+	// Zicbop prefetch.* are HINT instructions.
+	ksft_print_msg("Testing Zicbop instructions\n");
+
+	illegal = false;
+	prefetch_i(&mem[0]);
+	ksft_test_result(!illegal, "No prefetch.i\n");
+
+	illegal = false;
+	prefetch_r(&mem[0]);
+	ksft_test_result(!illegal, "No prefetch.r\n");
+
+	illegal = false;
+	prefetch_w(&mem[0]);
+	ksft_test_result(!illegal, "No prefetch.w\n");
+}
+
+static void test_zicbop(void *arg)
+{
+	struct riscv_hwprobe pair = {
+		.key = RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE,
+	};
+	cpu_set_t *cpus = (cpu_set_t *)arg;
+	__u64 block_size;
+	long rc;
+
+	rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)cpus, 0);
+	block_size = pair.value;
+	ksft_test_result(rc == 0 && pair.key == RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE &&
+			 is_power_of_2(block_size), "Zicbop block size\n");
+	ksft_print_msg("Zicbop block size: %llu\n", block_size);
+
+	illegal = false;
+	prefetch_i(&mem[0]);
+	prefetch_r(&mem[0]);
+	prefetch_w(&mem[0]);
+	ksft_test_result(!illegal, "Zicbop prefetch.* on valid address\n");
+
+	illegal = false;
+	prefetch_i(NULL);
+	prefetch_r(NULL);
+	prefetch_w(NULL);
+	ksft_test_result(!illegal, "Zicbop prefetch.* on NULL\n");
+}
+
+static void check_no_zicbop_cpus(cpu_set_t *cpus)
+{
+	struct riscv_hwprobe pair = {
+		.key = RISCV_HWPROBE_KEY_IMA_EXT_0,
+	};
+	cpu_set_t one_cpu;
+	int i = 0, c = 0;
+	long rc;
+
+	while (i++ < CPU_COUNT(cpus)) {
+		while (!CPU_ISSET(c, cpus))
+			++c;
+
+		CPU_ZERO(&one_cpu);
+		CPU_SET(c, &one_cpu);
+
+		rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&one_cpu, 0);
+		assert(rc == 0 && pair.key == RISCV_HWPROBE_KEY_IMA_EXT_0);
+
+		if (pair.value & RISCV_HWPROBE_EXT_ZICBOP)
+			ksft_exit_fail_msg("zicbop is only present on a subset of harts.\n"
+					   "Use taskset to select a set of harts where zicbop\n"
+					   "presence (present or not) is consistent for each hart\n");
+		++c;
+	}
+}
+
+enum {
+	TEST_ZICBOP,
+	TEST_NO_ZICBOP,
+};
+
+enum {
+	HANDLER_SIGILL,
+	HANDLER_SIGSEGV,
+	HANDLER_SIGBUS,
+};
+
+static struct test_info {
+	bool enabled;
+	unsigned int nr_tests;
+	void (*test_fn)(void *arg);
+} tests[] = {
+	[TEST_ZICBOP]		= { .nr_tests = 3, test_zicbop },
+	[TEST_NO_ZICBOP]	= { .nr_tests = 3, test_no_zicbop },
+};
+
+static struct sighandler_info {
+	const char *flag;
+	int sig;
+} handlers[] = {
+	[HANDLER_SIGILL] = { .flag = "--sigill", .sig = SIGILL },
+	[HANDLER_SIGSEGV] = { .flag = "--sigsegv", .sig = SIGSEGV },
+	[HANDLER_SIGBUS] = { .flag = "--sigbus", .sig = SIGBUS },
+};
+
+static bool search_flag(int argc, char **argv, const char *flag)
+{
+	int i;
+
+	for (i = 1; i < argc; i++) {
+		if (!strcmp(argv[i], flag))
+			return true;
+	}
+	return false;
+}
+
+static void install_sigaction(int argc, char **argv)
+{
+	int i, rc;
+	struct sigaction act = {
+		.sa_sigaction = &sigill_handler,
+		.sa_flags = SA_SIGINFO,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(handlers); ++i) {
+		if (search_flag(argc, argv, handlers[i].flag)) {
+			rc = sigaction(handlers[i].sig, &act, NULL);
+			assert(rc == 0);
+		}
+	}
+
+	if (search_flag(argc, argv, handlers[HANDLER_SIGILL].flag))
+		tests[TEST_NO_ZICBOP].enabled = true;
+}
+
+int main(int argc, char **argv)
+{
+	struct riscv_hwprobe pair;
+	unsigned int plan = 0;
+	cpu_set_t cpus;
+	long rc;
+	int i;
+
+	install_sigaction(argc, argv);
+
+	rc = sched_getaffinity(0, sizeof(cpu_set_t), &cpus);
+	assert(rc == 0);
+
+	ksft_print_header();
+
+	pair.key = RISCV_HWPROBE_KEY_IMA_EXT_0;
+	rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&cpus, 0);
+	if (rc < 0)
+		ksft_exit_fail_msg("hwprobe() failed with %ld\n", rc);
+	assert(rc == 0 && pair.key == RISCV_HWPROBE_KEY_IMA_EXT_0);
+
+	if (pair.value & RISCV_HWPROBE_EXT_ZICBOP)
+		tests[TEST_ZICBOP].enabled = true;
+	else
+		check_no_zicbop_cpus(&cpus);
+
+	for (i = 0; i < ARRAY_SIZE(tests); ++i)
+		plan += tests[i].enabled ? tests[i].nr_tests : 0;
+
+	if (plan == 0)
+		ksft_print_msg("No tests enabled.\n");
+	else
+		ksft_set_plan(plan);
+
+	for (i = 0; i < ARRAY_SIZE(tests); ++i) {
+		if (tests[i].enabled)
+			tests[i].test_fn(&cpus);
+	}
+
+	ksft_finished();
+}
-- 
2.47.2


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Re: [PATCH v2 4/4] selftests/riscv: Add Zicbop prefetch test

[Andrew Jones]

On Thu, Oct 09, 2025 at 09:41:54PM +0800, Yao Zihong wrote:
> Add a new selftest under hwprobe/ to verify Zicbop extension behavior.
> 
> The test checks:
> - That hwprobe correctly reports Zicbop presence and block size.
> - That prefetch instructions execute without exception on valid and NULL
>   addresses when Zicbop is present.
> - That prefetch.{i,r,w} do not trigger SIGILL even when Zicbop is absent,
>   since Zicbop instructions are defined as hints.
> 
> The test is based on cbo.c but adapted for Zicbop prefetch instructions.
> 
> Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
> ---
>  .../testing/selftests/riscv/hwprobe/Makefile  |   5 +-
>  .../selftests/riscv/hwprobe/prefetch.c        | 236 ++++++++++++++++++
>  2 files changed, 240 insertions(+), 1 deletion(-)
>  create mode 100644 tools/testing/selftests/riscv/hwprobe/prefetch.c
> 
> diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing/selftests/riscv/hwprobe/Makefile
> index cec81610a5f2..3c8b8ba7629c 100644
> --- a/tools/testing/selftests/riscv/hwprobe/Makefile
> +++ b/tools/testing/selftests/riscv/hwprobe/Makefile
> @@ -4,7 +4,7 @@
>  
>  CFLAGS += -I$(top_srcdir)/tools/include
>  
> -TEST_GEN_PROGS := hwprobe cbo which-cpus
> +TEST_GEN_PROGS := hwprobe cbo which-cpus prefetch
>  
>  include ../../lib.mk
>  
> @@ -16,3 +16,6 @@ $(OUTPUT)/cbo: cbo.c sys_hwprobe.S
>  
>  $(OUTPUT)/which-cpus: which-cpus.c sys_hwprobe.S
>  	$(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^
> +
> +$(OUTPUT)/prefetch: prefetch.c sys_hwprobe.S
> +	$(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^
> diff --git a/tools/testing/selftests/riscv/hwprobe/prefetch.c b/tools/testing/selftests/riscv/hwprobe/prefetch.c
> new file mode 100644
> index 000000000000..d9ea048325fb
> --- /dev/null
> +++ b/tools/testing/selftests/riscv/hwprobe/prefetch.c
> @@ -0,0 +1,236 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023 Ventana Micro Systems Inc.
> + * Copyright (c) 2025 PLCT Lab, ISCAS
> + *
> + * Based on tools/testing/selftests/riscv/hwprobe/cbo.c with modifications
> + * for Zicbop prefetch testing.
> + *
> + * Run with 'taskset -c <cpu-list> prefetch' to only execute hwprobe on a
> + * subset of cpus, as well as only executing the tests on those cpus.
> + */
> +#define _GNU_SOURCE
> +#include <stdbool.h>
> +#include <stdint.h>
> +#include <string.h>
> +#include <sched.h>
> +#include <signal.h>
> +#include <assert.h>
> +#include <linux/compiler.h>
> +#include <linux/kernel.h>
> +#include <asm/ucontext.h>
> +
> +#include "hwprobe.h"
> +#include "../../kselftest.h"
> +
> +#define MK_PREFETCH(fn) \
> +	le32_bswap(0 << 25 | (uint32_t)(fn) << 20 | 10 << 15 | 6 << 12 | 0 << 7 | 19)
> +
> +static char mem[4096] __aligned(4096) = { [0 ... 4095] = 0xa5 };
> +
> +static bool illegal;
> +
> +static void sigill_handler(int sig, siginfo_t *info, void *context)
> +{
> +	unsigned long *regs = (unsigned long *)&((ucontext_t *)context)->uc_mcontext;
> +	uint32_t insn = *(uint32_t *)regs[0];
> +
> +	assert(insn == MK_PREFETCH(regs[11]));
> +
> +	illegal = true;
> +	regs[0] += 4;
> +}
> +
> +#define prefetch_insn(base, fn)							\
> +({										\
> +	asm volatile(								\
> +	"mv	a0, %0\n"							\
> +	"li	a1, %1\n"							\
> +	".4byte	%2\n"								\
> +	: : "r" (base), "i" (fn), "i" (MK_PREFETCH(fn)) : "a0", "a1", "memory");\
> +})
> +
> +static void prefetch_i(char *base) { prefetch_insn(base, 0); }
> +
> +static void prefetch_r(char *base) { prefetch_insn(base, 1); }
> +
> +static void prefetch_w(char *base) { prefetch_insn(base, 3); }

Please remove the unnecessary blank lines between function definitions.

> +
> +static bool is_power_of_2(__u64 n)
> +{
> +	return n != 0 && (n & (n - 1)) == 0;
> +}
> +
> +static void test_no_zicbop(void *arg)
> +{
> +	// Zicbop prefetch.* are HINT instructions.

No C++ comments. Run checkpatch.

> +	ksft_print_msg("Testing Zicbop instructions\n");
> +
> +	illegal = false;
> +	prefetch_i(&mem[0]);
> +	ksft_test_result(!illegal, "No prefetch.i\n");
> +
> +	illegal = false;
> +	prefetch_r(&mem[0]);
> +	ksft_test_result(!illegal, "No prefetch.r\n");
> +
> +	illegal = false;
> +	prefetch_w(&mem[0]);
> +	ksft_test_result(!illegal, "No prefetch.w\n");
> +}
> +
> +static void test_zicbop(void *arg)
> +{
> +	struct riscv_hwprobe pair = {
> +		.key = RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE,
> +	};
> +	cpu_set_t *cpus = (cpu_set_t *)arg;
> +	__u64 block_size;
> +	long rc;
> +
> +	rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)cpus, 0);
> +	block_size = pair.value;
> +	ksft_test_result(rc == 0 && pair.key == RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE &&
> +			 is_power_of_2(block_size), "Zicbop block size\n");
> +	ksft_print_msg("Zicbop block size: %llu\n", block_size);
> +
> +	illegal = false;
> +	prefetch_i(&mem[0]);
> +	prefetch_r(&mem[0]);
> +	prefetch_w(&mem[0]);
> +	ksft_test_result(!illegal, "Zicbop prefetch.* on valid address\n");
> +
> +	illegal = false;
> +	prefetch_i(NULL);
> +	prefetch_r(NULL);
> +	prefetch_w(NULL);
> +	ksft_test_result(!illegal, "Zicbop prefetch.* on NULL\n");
> +}
> +
> +static void check_no_zicbop_cpus(cpu_set_t *cpus)
> +{
> +	struct riscv_hwprobe pair = {
> +		.key = RISCV_HWPROBE_KEY_IMA_EXT_0,
> +	};
> +	cpu_set_t one_cpu;
> +	int i = 0, c = 0;
> +	long rc;
> +
> +	while (i++ < CPU_COUNT(cpus)) {
> +		while (!CPU_ISSET(c, cpus))
> +			++c;
> +
> +		CPU_ZERO(&one_cpu);
> +		CPU_SET(c, &one_cpu);
> +
> +		rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&one_cpu, 0);
> +		assert(rc == 0 && pair.key == RISCV_HWPROBE_KEY_IMA_EXT_0);
> +
> +		if (pair.value & RISCV_HWPROBE_EXT_ZICBOP)
> +			ksft_exit_fail_msg("zicbop is only present on a subset of harts.\n"
> +					   "Use taskset to select a set of harts where zicbop\n"
> +					   "presence (present or not) is consistent for each hart\n");
> +		++c;
> +	}
> +}
> +
> +enum {
> +	TEST_ZICBOP,
> +	TEST_NO_ZICBOP,
> +};
> +
> +enum {
> +	HANDLER_SIGILL,
> +	HANDLER_SIGSEGV,
> +	HANDLER_SIGBUS,
> +};

Why create this enum?

> +
> +static struct test_info {
> +	bool enabled;
> +	unsigned int nr_tests;
> +	void (*test_fn)(void *arg);
> +} tests[] = {
> +	[TEST_ZICBOP]		= { .nr_tests = 3, test_zicbop },
> +	[TEST_NO_ZICBOP]	= { .nr_tests = 3, test_no_zicbop },
> +};
> +
> +static struct sighandler_info {
> +	const char *flag;
> +	int sig;
> +} handlers[] = {
> +	[HANDLER_SIGILL] = { .flag = "--sigill", .sig = SIGILL },
> +	[HANDLER_SIGSEGV] = { .flag = "--sigsegv", .sig = SIGSEGV },
> +	[HANDLER_SIGBUS] = { .flag = "--sigbus", .sig = SIGBUS },
> +};
> +
> +static bool search_flag(int argc, char **argv, const char *flag)
> +{
> +	int i;
> +
> +	for (i = 1; i < argc; i++) {
> +		if (!strcmp(argv[i], flag))
> +			return true;
> +	}
> +	return false;
> +}

Instead of this search function just use getopt()

> +
> +static void install_sigaction(int argc, char **argv)
> +{
> +	int i, rc;
> +	struct sigaction act = {
> +		.sa_sigaction = &sigill_handler,
> +		.sa_flags = SA_SIGINFO,
> +	};
> +
> +	for (i = 0; i < ARRAY_SIZE(handlers); ++i) {
> +		if (search_flag(argc, argv, handlers[i].flag)) {
> +			rc = sigaction(handlers[i].sig, &act, NULL);
> +			assert(rc == 0);
> +		}
> +	}
> +
> +	if (search_flag(argc, argv, handlers[HANDLER_SIGILL].flag))
> +		tests[TEST_NO_ZICBOP].enabled = true;
> +}
> +
> +int main(int argc, char **argv)
> +{
> +	struct riscv_hwprobe pair;
> +	unsigned int plan = 0;
> +	cpu_set_t cpus;
> +	long rc;
> +	int i;
> +
> +	install_sigaction(argc, argv);
> +
> +	rc = sched_getaffinity(0, sizeof(cpu_set_t), &cpus);
> +	assert(rc == 0);
> +
> +	ksft_print_header();
> +
> +	pair.key = RISCV_HWPROBE_KEY_IMA_EXT_0;
> +	rc = riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&cpus, 0);
> +	if (rc < 0)
> +		ksft_exit_fail_msg("hwprobe() failed with %ld\n", rc);
> +	assert(rc == 0 && pair.key == RISCV_HWPROBE_KEY_IMA_EXT_0);
> +
> +	if (pair.value & RISCV_HWPROBE_EXT_ZICBOP)
> +		tests[TEST_ZICBOP].enabled = true;
> +	else
> +		check_no_zicbop_cpus(&cpus);
> +
> +	for (i = 0; i < ARRAY_SIZE(tests); ++i)
> +		plan += tests[i].enabled ? tests[i].nr_tests : 0;
> +
> +	if (plan == 0)
> +		ksft_print_msg("No tests enabled.\n");
> +	else
> +		ksft_set_plan(plan);
> +
> +	for (i = 0; i < ARRAY_SIZE(tests); ++i) {
> +		if (tests[i].enabled)
> +			tests[i].test_fn(&cpus);
> +	}
> +
> +	ksft_finished();
> +}
> -- 
> 2.47.2
>

There's no reason to duplicate cbo.c. Just parameterize
check_no_zicboz_cpus() (and rename it to check_no_zicbo_cpus())
in order to share it with zicbop and then add your new tests.

drew

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Re: [PATCH v2 4/4] selftests/riscv: Add Zicbop prefetch test

[Yao Zihong]

Thanks for the review, I’ll fix those issues in the next revision.

Also, do you think it’s worth renaming cbo.c to something more generic
(like zicbo.c), or should I keep the current name for consistency?

Thanks,
Zihong


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Re: [PATCH v2 4/4] selftests/riscv: Add Zicbop prefetch test

[Andrew Jones]

On Tue, Oct 14, 2025 at 12:16:41AM +0800, Yao Zihong wrote:
> Thanks for the review, I’ll fix those issues in the next revision.
> 
> Also, do you think it’s worth renaming cbo.c to something more generic
> (like zicbo.c), or should I keep the current name for consistency?

The cbo (cache-block operations) name represents all the cbo.*
instructions and all the prefetch.* instructions, just as section 2.2
"Cache-Block Operations" of the CMO spec introduces all of them under
the same heading.

Thanks,
drew

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Re: [PATCH v2 0/4] riscv: hwprobe: Add Zicbop support

[Andrew Jones]

On Thu, Oct 09, 2025 at 09:41:50PM +0800, Yao Zihong wrote:
> Changes since v1:
> ------------------
> - Bump RISCV_HWPROBE_MAX_KEY (modified 1/4).
> - Add documentation for the Zicbop hwprobe bit/key (new 3/4).
> - Add a selftest(prefetch.c) for Zicbop (new 4/4).
> 
> Add UAPI and kernel plumbing to expose the Zicbop extension presence
> and its block size through hwprobe. The interface mirrors
> Zicbom/Zicboz. This allows userspace to safely discover and optimize
> for Zicbop when available.
> 
> Background: Zicbop is mandated by the RVA22U64 profile. Downstream may
> combine the presence bit with ZICBOP_BLOCK_SIZE to make profile-level
> policy decisions or enable Zicbop-specific optimizations.
> 
> Yao Zihong (4):
>   uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key
>   riscv: hwprobe: Report Zicbop presence and block size
>   docs: riscv: Document hwprobe for Zicbop
>   selftests/riscv: Add Zicbop prefetch test
> 
>  Documentation/arch/riscv/hwprobe.rst          |   8 +-
>  arch/riscv/include/asm/hwprobe.h              |   2 +-
>  arch/riscv/include/uapi/asm/hwprobe.h         |   2 +
>  arch/riscv/kernel/sys_hwprobe.c               |   6 +
>  .../testing/selftests/riscv/hwprobe/Makefile  |   5 +-
>  .../selftests/riscv/hwprobe/prefetch.c        | 236 ++++++++++++++++++
>  6 files changed, 256 insertions(+), 3 deletions(-)
>  create mode 100644 tools/testing/selftests/riscv/hwprobe/prefetch.c
> 
> -- 
> 2.47.2
>

I'm not sure why patches 1-3 aren't just squashed together like commit
eb1003970940 ("RISC-V: hwprobe: Expose Zicbom extension and its block
size") does for zicbom.

Thanks,
drew

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Re: [PATCH v2 0/4] riscv: hwprobe: Add Zicbop support

[Yao Zihong]

I found that there are a few different styles in the tree, but
following the Zicbom example would indeed be cleaner.

I’ll squash 1-3 together in v3 for simplicity and consistency.

Thanks,
Zihong


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