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From: Alex Elder <elder@riscstar.com>
To: han.xu@nxp.com, broonie@kernel.org
Cc: dlan@gentoo.org, Frank.li@nxp.com, guodong@riscstar.com,
	linux-spi@vger.kernel.org, imx@lists.linux.dev,
	spacemit@lists.linux.dev, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, Frank Li <Frank.Li@nxp.com>
Subject: [PATCH v4 6/9] spi: fsl-qspi: introduce sfa_size devtype data
Date: Mon, 27 Oct 2025 08:30:04 -0500	[thread overview]
Message-ID: <20251027133008.360237-7-elder@riscstar.com> (raw)
In-Reply-To: <20251027133008.360237-1-elder@riscstar.com>

In fsl_qspi_default_setup(), four registers define the size of blocks of
data to written to each of four chips that comprise SPI NOR flash storage.
They are currently defined to be the same as the AHB buffer size.

The SpacemiT QSPI has an AHB buffer size of 512 bytes, but requires these
four sizes to be multiples of 1024 bytes.

Define a new field sfa_size in the fsl_qspi_devtype_data structure that, if
non-zero, will be used instead of the AHB buffer size to define the size of
these chip regions.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
---
 drivers/spi/spi-fsl-qspi.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index 2c030dd6facc7..46a3187b33548 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -207,6 +207,7 @@ struct fsl_qspi_devtype_data {
 	unsigned int txfifo;
 	int invalid_mstrid;
 	unsigned int ahb_buf_size;
+	unsigned int sfa_size;
 	unsigned int quirks;
 	bool little_endian;
 };
@@ -737,6 +738,7 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
 {
 	void __iomem *base = q->iobase;
 	u32 reg, addr_offset = 0;
+	u32 sfa_size;
 	int ret;
 
 	/* disable and unprepare clock to avoid glitch pass to controller */
@@ -795,17 +797,17 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
 	 * In HW there can be a maximum of four chips on two buses with
 	 * two chip selects on each bus. We use four chip selects in SW
 	 * to differentiate between the four chips.
-	 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
-	 * SFB2AD accordingly.
+	 *
+	 * By default we write the AHB buffer size to each chip, but
+	 * a different size can be specified with devtype_data->sfa_size.
+	 * The SFA1AD, SFA2AD, SFB1AD, and SFB2AD registers define the
+	 * top (end) of these four regions.
 	 */
-	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
-		    base + QUADSPI_SFA1AD);
-	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
-		    base + QUADSPI_SFA2AD);
-	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
-		    base + QUADSPI_SFB1AD);
-	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
-		    base + QUADSPI_SFB2AD);
+	sfa_size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size;
+	qspi_writel(q, addr_offset + 1 * sfa_size, base + QUADSPI_SFA1AD);
+	qspi_writel(q, addr_offset + 2 * sfa_size, base + QUADSPI_SFA2AD);
+	qspi_writel(q, addr_offset + 3 * sfa_size, base + QUADSPI_SFB1AD);
+	qspi_writel(q, addr_offset + 4 * sfa_size, base + QUADSPI_SFB2AD);
 
 	q->selected = -1;
 
-- 
2.48.1


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  parent reply	other threads:[~2025-10-27 13:30 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-27 13:29 [PATCH v4 0/9] spi: enable the SpacemiT K1 SoC QSPI Alex Elder
2025-10-27 13:29 ` [PATCH v4 1/9] dt-bindings: spi: fsl-qspi: support SpacemiT K1 Alex Elder
2025-11-06 16:55   ` Mark Brown
2025-10-27 13:30 ` [PATCH v4 2/9] dt-bindings: spi: fsl-qspi: add optional resets Alex Elder
2025-10-27 13:30 ` [PATCH v4 3/9] spi: fsl-qspi: add optional reset support Alex Elder
2025-10-27 13:30 ` [PATCH v4 4/9] spi: fsl-qspi: switch predicates to bool Alex Elder
2025-10-27 13:30 ` [PATCH v4 5/9] spi: fsl-qspi: add a clock disable quirk Alex Elder
2025-10-27 13:30 ` Alex Elder [this message]
2025-10-27 13:30 ` [PATCH v4 7/9] spi: fsl-qspi: support the SpacemiT K1 SoC Alex Elder
2025-10-27 13:30 ` [PATCH v4 8/9] riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3 Alex Elder
2025-10-27 13:30 ` [PATCH v4 9/9] riscv: defconfig: enable SPI_FSL_QUADSPI as a module Alex Elder
2025-11-12 11:19   ` Yixun Lan
2025-11-07 10:15 ` (subset) [PATCH v4 0/9] spi: enable the SpacemiT K1 SoC QSPI Mark Brown
2025-11-12 10:23 ` Yixun Lan
2025-11-12 18:56 ` Conor Dooley

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