From: Conor Dooley <conor@kernel.org>
To: Yunhui Cui <cuiyunhui@bytedance.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, luxu.kernel@bytedance.com,
atishp@rivosinc.com, cleger@rivosinc.com,
ajones@ventanamicro.com, apatel@ventanamicro.com,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
songshuaishuai@tinylab.org, bjorn@rivosinc.com,
charlie@rivosinc.com, masahiroy@kernel.org,
valentina.fernandezalanis@microchip.com,
jassisinghbrar@gmail.com, conor.dooley@microchip.com
Subject: Re: [PATCH 1/3] drivers: firmware: riscv: add SSE NMI support
Date: Tue, 28 Oct 2025 10:53:40 +0000 [thread overview]
Message-ID: <20251028-foam-hypocrite-f37fe270115d@spud> (raw)
In-Reply-To: <20251027133431.15321-2-cuiyunhui@bytedance.com>
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On Mon, Oct 27, 2025 at 09:34:29PM +0800, Yunhui Cui wrote:
> Add support for handling Non-Maskable Interrupts (NMIs) through the
> RISC-V Supervisor Software Events (SSE) framework. Since each NMI
> type(e.g., unknown NMI, etc.) requires a distinct SSE event, a newfile
> sse_nmi.c is introduced to manage their registration and enabling.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> ---
> MAINTAINERS | 7 +++
> arch/riscv/include/asm/sbi.h | 1 +
> drivers/firmware/riscv/Kconfig | 10 ++++
> drivers/firmware/riscv/Makefile | 1 +
> drivers/firmware/riscv/sse_nmi.c | 81 ++++++++++++++++++++++++++++++++
> 5 files changed, 100 insertions(+)
> create mode 100644 drivers/firmware/riscv/sse_nmi.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8bf5416953f45..6df6cbec4d85d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -22057,6 +22057,13 @@ S: Maintained
> F: drivers/firmware/riscv/riscv_sse.c
> F: include/linux/riscv_sse.h
>
> +RISC-V SSE NMI SUPPORT
> +M: Yunhui Cui <cuiyunhui@bytedance.com>
> +R: Xu Lu <luxu.kernel@bytedance.com>
> +L: linux-riscv@lists.infradead.org
> +S: Maintained
> +F: drivers/firmware/riscv/sse_nmi.c
Does actually this need a separate entry?
> RISC-V THEAD SoC SUPPORT
> M: Drew Fustini <fustini@kernel.org>
> M: Guo Ren <guoren@kernel.org>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 874cc1d7603a5..52d3fdf2d4cc1 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -486,6 +486,7 @@ enum sbi_sse_attr_id {
> #define SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS 0x00100000
> #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS 0x00108000
> #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED 0xffff0000
> +#define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI 0xffff0001
Where is this canonically defined?
I looked at the v3 SBI spec and it says:
0xffff0001 - 0xffff3fff Local events reserved for future use
This needs to be marked RFC until this event is in a frozen version of
the SBI spec.
> #define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED 0xffff8000
>
> #define SBI_SSE_EVENT_PLATFORM BIT(14)
> diff --git a/drivers/firmware/riscv/Kconfig b/drivers/firmware/riscv/Kconfig
> index ed5b663ac5f91..fd16b4c43cf01 100644
> --- a/drivers/firmware/riscv/Kconfig
> +++ b/drivers/firmware/riscv/Kconfig
> @@ -12,4 +12,14 @@ config RISCV_SBI_SSE
> this option provides support to register callbacks on specific SSE
> events.
>
> +config RISCV_SSE_NMI
I think I'd like to see both the filename and Kconfig option match the
established naming for the base sse support.
> + bool "Enable SBI Supervisor Software Events NMI support"
> + depends on RISCV_SBI_SSE
> + default y
> + help
> + This option enables support for delivering Non-Maskable Interrupt
> + (NMI) notifications through the Supervisor Software Events (SSE)
> + framework.
> When enabled, the system supports some common NMI features
> + such as unknown NMI handling.
No, when enabled the _kernel_ supports these things. The code in this
patch seems to fail gracefully when there's no SSE support in the
underlying system, but you should make the option description match
reality.
Cheers,
Conor.
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next prev parent reply other threads:[~2025-10-28 10:53 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-27 13:34 [PATCH 0/3] Add NMI Support to RISC-V via SSE Yunhui Cui
2025-10-27 13:34 ` [PATCH 1/3] drivers: firmware: riscv: add SSE NMI support Yunhui Cui
2025-10-28 10:53 ` Conor Dooley [this message]
2025-10-27 13:34 ` [PATCH 2/3] riscv: crash: move IPI crash handling logic to crash.c Yunhui Cui
2025-10-27 13:34 ` [PATCH 3/3] riscv: crash: use NMI to stop the CPU Yunhui Cui
2025-10-28 10:42 ` Conor Dooley
2025-10-28 12:36 ` Radim Krčmář
2025-11-03 14:10 ` [External] " yunhui cui
2025-11-03 17:23 ` Radim Krčmář
2025-11-03 13:36 ` yunhui cui
2025-10-30 8:46 ` Atish Patra
2025-10-31 1:24 ` Bagas Sanjaya
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