From: Bagas Sanjaya <bagasdotme@gmail.com>
To: Atish Patra <atish.patra@linux.dev>,
Yunhui Cui <cuiyunhui@bytedance.com>,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, conor@kernel.org,
luxu.kernel@bytedance.com, cleger@rivosinc.com,
ajones@ventanamicro.com, apatel@ventanamicro.com,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
songshuaishuai@tinylab.org, bjorn@rivosinc.com,
charlie@rivosinc.com, masahiroy@kernel.org,
valentina.fernandezalanis@microchip.com,
jassisinghbrar@gmail.com, conor.dooley@microchip.com
Subject: Re: [PATCH 3/3] riscv: crash: use NMI to stop the CPU
Date: Fri, 31 Oct 2025 08:24:25 +0700 [thread overview]
Message-ID: <aQQPyan9ifX84e4h@archie.me> (raw)
In-Reply-To: <e9c2021a-fa7f-4b01-9b48-afe5fa73135f@linux.dev>
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On Thu, Oct 30, 2025 at 01:46:40AM -0700, Atish Patra wrote:
> 1. Invoking SSE on this path may lead to some race conditions if
> interruption is enabled.
What race condition?
Confused...
--
An old man doll... just what I always wanted! - Clara
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prev parent reply other threads:[~2025-10-31 1:24 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-27 13:34 [PATCH 0/3] Add NMI Support to RISC-V via SSE Yunhui Cui
2025-10-27 13:34 ` [PATCH 1/3] drivers: firmware: riscv: add SSE NMI support Yunhui Cui
2025-10-28 10:53 ` Conor Dooley
2025-10-27 13:34 ` [PATCH 2/3] riscv: crash: move IPI crash handling logic to crash.c Yunhui Cui
2025-10-27 13:34 ` [PATCH 3/3] riscv: crash: use NMI to stop the CPU Yunhui Cui
2025-10-28 10:42 ` Conor Dooley
2025-10-28 12:36 ` Radim Krčmář
2025-11-03 14:10 ` [External] " yunhui cui
2025-11-03 17:23 ` Radim Krčmář
2025-11-03 13:36 ` yunhui cui
2025-10-30 8:46 ` Atish Patra
2025-10-31 1:24 ` Bagas Sanjaya [this message]
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