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From: Xu Lu <luxu.kernel@bytedance.com>
To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, apatel@ventanamicro.com, guoren@kernel.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Xu Lu <luxu.kernel@bytedance.com>
Subject: [RFC PATCH v1 2/4] riscv: mm: Introduce percpu tlb flush queue
Date: Thu, 30 Oct 2025 21:56:50 +0800	[thread overview]
Message-ID: <20251030135652.63837-3-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20251030135652.63837-1-luxu.kernel@bytedance.com>

The percpu tlb flush queue is used to buffer the tlb flush tasks that
each cpu needs to process.

Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
 arch/riscv/mm/tlbflush.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 8404530ec00f9..aa8f1304ae5c4 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -103,6 +103,18 @@ struct flush_tlb_range_data {
 	unsigned long stride;
 };
 
+#define TLB_FLUSH_QUEUE_SIZE					16
+struct tlb_flush_queue {
+	struct flush_tlb_range_data tasks[TLB_FLUSH_QUEUE_SIZE];
+	raw_spinlock_t lock;
+	unsigned int len;
+};
+
+DEFINE_PER_CPU(struct tlb_flush_queue, tlb_flush_queue) = {
+	.lock = __RAW_SPIN_LOCK_UNLOCKED(tlb_flush_queue.lock),
+	.len = 0,
+};
+
 static void __ipi_flush_tlb_range_asid(void *info)
 {
 	struct flush_tlb_range_data *d = info;
-- 
2.20.1


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  parent reply	other threads:[~2025-10-30 13:57 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-30 13:56 [RFC PATCH v1 0/4] riscv: mm: Defer tlb flush to context_switch Xu Lu
2025-10-30 13:56 ` [RFC PATCH v1 1/4] riscv: mm: Introduce percpu loaded_asid Xu Lu
2025-10-30 13:56 ` Xu Lu [this message]
2025-10-30 13:56 ` [RFC PATCH v1 3/4] riscv: mm: Enqueue tlbflush info if task is not running on target cpu Xu Lu
2025-10-30 13:56 ` [RFC PATCH v1 4/4] riscv: mm: Perform tlb flush during context_switch Xu Lu
2025-11-03  3:44   ` Guo Ren
2025-11-03  3:44 ` [RFC PATCH v1 0/4] riscv: mm: Defer tlb flush to context_switch Guo Ren
2025-11-03  7:06   ` [External] " Xu Lu
2025-11-07  1:55 ` Guo Ren
2025-11-07  3:03   ` [External] " Xu Lu

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