[PATCH v1 1/4] MAINTAINERS: add Conor to StarFive entry

[PATCH v1 1/4] MAINTAINERS: add Conor to StarFive entry

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

I apply the patches for StarFive devicetrees, add me to the entry along
with my tree location etc. This is not a functional change, as this info
was in the "RISC-V MISC" entry but I'd rather not have the duplication
of entries covering the StarFive directory.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 MAINTAINERS | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 24efae3df425..a0e092d2d88a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22122,7 +22122,6 @@ T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
 F:	arch/riscv/boot/dts/canaan/
 F:	arch/riscv/boot/dts/microchip/
 F:	arch/riscv/boot/dts/sifive/
-F:	arch/riscv/boot/dts/starfive/
 
 RISC-V PMU DRIVERS
 M:	Atish Patra <atish.patra@linux.dev>
@@ -24447,7 +24446,10 @@ F:	drivers/crypto/starfive/
 
 STARFIVE DEVICETREES
 M:	Emil Renner Berthing <kernel@esmil.dk>
+M:	Conor Dooley <conor@kernel.org>
+L:	linux-riscv@lists.infradead.org
 S:	Maintained
+T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
 F:	arch/riscv/boot/dts/starfive/
 
 STARFIVE DWMAC GLUE LAYER
-- 
2.51.0


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[PATCH v1 2/4] MAINTAINERS: remove patchwork from RISC-V MISC SOC SUPPORT

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

I don't use the main riscv patchwork for anything to do with SoCs,
remove them from here to avoid confusion.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 MAINTAINERS | 1 -
 1 file changed, 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a0e092d2d88a..0836b5422826 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22117,7 +22117,6 @@ RISC-V MISC SOC SUPPORT
 M:	Conor Dooley <conor@kernel.org>
 L:	linux-riscv@lists.infradead.org
 S:	Maintained
-Q:	https://patchwork.kernel.org/project/linux-riscv/list/
 T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
 F:	arch/riscv/boot/dts/canaan/
 F:	arch/riscv/boot/dts/microchip/
-- 
2.51.0


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[PATCH v1 3/4] MAINTAINERS: add tree to RISC-V Microchip entry

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

In fairness to my own employer, lumping it in as "misc" is not quite
accurate when they do pay me to look after the platform. Move the tree
link for it to its entry, rather than having the RISC-V MISC SOC SUPPORT
entry cover it.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0836b5422826..e5e4bcf7a408 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22084,6 +22084,7 @@ M:	Conor Dooley <conor.dooley@microchip.com>
 M:	Daire McNamara <daire.mcnamara@microchip.com>
 L:	linux-riscv@lists.infradead.org
 S:	Supported
+T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ (dts, soc, firmware)
 F:	Documentation/devicetree/bindings/clock/microchip,mpfs*.yaml
 F:	Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
 F:	Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
@@ -22119,7 +22120,6 @@ L:	linux-riscv@lists.infradead.org
 S:	Maintained
 T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
 F:	arch/riscv/boot/dts/canaan/
-F:	arch/riscv/boot/dts/microchip/
 F:	arch/riscv/boot/dts/sifive/
 
 RISC-V PMU DRIVERS
-- 
2.51.0


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[PATCH v1 4/4] MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

The SiFive and Canaan platforms are not being actively looked after at
this point, but fixes for them would be applied if/when the patches
appeared. Since they're now the only things in the RISC-V MISC SOC
SUPPORT, mark them as Odd Fixes. I don't believe this is a functional
change, it just represents what's actually happening - particularly
since the Canaan k230 never built up enough steam to get merged and the
new SiFive demo chips have been done in partnership with with other
companies, e.g. Eswin, and will reside in their directories instead.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index e5e4bcf7a408..735f5447c52d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22117,7 +22117,7 @@ F:	include/soc/microchip/mpfs.h
 RISC-V MISC SOC SUPPORT
 M:	Conor Dooley <conor@kernel.org>
 L:	linux-riscv@lists.infradead.org
-S:	Maintained
+S:	Odd Fixes
 T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
 F:	arch/riscv/boot/dts/canaan/
 F:	arch/riscv/boot/dts/sifive/
-- 
2.51.0


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Re: [PATCH v1 4/4] MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes

[Paul Walmsley]

On Sun, 23 Nov 2025, Conor Dooley wrote:

> From: Conor Dooley <conor.dooley@microchip.com>
> 
> The SiFive and Canaan platforms are not being actively looked after at
> this point, but fixes for them would be applied if/when the patches
> appeared. Since they're now the only things in the RISC-V MISC SOC
> SUPPORT, mark them as Odd Fixes. I don't believe this is a functional
> change, it just represents what's actually happening - particularly
> since the Canaan k230 never built up enough steam to get merged and the
> new SiFive demo chips have been done in partnership with with other
> companies, e.g. Eswin, and will reside in their directories instead.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Paul Walmsley <pjw@kernel.org>

- Paul


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Re: [PATCH v1 1/4] MAINTAINERS: add Conor to StarFive entry

[Emil Renner Berthing]

Quoting Conor Dooley (2025-11-23 19:53:40)
> From: Conor Dooley <conor.dooley@microchip.com>
>
> I apply the patches for StarFive devicetrees, add me to the entry along
> with my tree location etc. This is not a functional change, as this info
> was in the "RISC-V MISC" entry but I'd rather not have the duplication
> of entries covering the StarFive directory.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Thanks for updating this to match the actual workflow.

Acked-by: Emil Renner Berthing <kernel@esmil.dk>

/Emil

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Re: [PATCH v1 1/4] MAINTAINERS: add Conor to StarFive entry

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

On Sun, 23 Nov 2025 18:53:40 +0000, Conor Dooley wrote:
> I apply the patches for StarFive devicetrees, add me to the entry along
> with my tree location etc. This is not a functional change, as this info
> was in the "RISC-V MISC" entry but I'd rather not have the duplication
> of entries covering the StarFive directory.
> 
> 

Putting these on the dt branch makes the most sense I think.

[1/4] MAINTAINERS: add Conor to StarFive entry
      https://git.kernel.org/conor/c/d15cd50d1444
[2/4] MAINTAINERS: remove patchwork from RISC-V MISC SOC SUPPORT
      https://git.kernel.org/conor/c/d794a761c77b
[3/4] MAINTAINERS: add tree to RISC-V Microchip entry
      https://git.kernel.org/conor/c/76cc0ba2af91
[4/4] MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes
      https://git.kernel.org/conor/c/56dfdf2da1cf

Thanks,
Conor.

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