From: Conor Dooley <conor@kernel.org>
To: Lv Zheng <lv.zheng@linux.spacemit.com>
Cc: Tomasz Jeznach <tjeznach@rivosinc.com>,
Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Jingyu Li <joey.li@spacemit.com>,
Zhijian Chen <zhijian@spacemit.com>,
iommu@lists.linux.dev, linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
devicetree@vger.kernel.org
Subject: Re: [PATCH v3 8/8] perf vendor events riscv:: Add support for spacemit,riscv-iommu HPM aliasing
Date: Wed, 4 Feb 2026 17:38:15 +0000 [thread overview]
Message-ID: <20260204-suds-shush-d85872589cb3@spud> (raw)
In-Reply-To: <5242DDF0A783AF08+e141f1898581018f8dd0723cb5c870c23ec679d6.1770195980.git.lv.zheng@linux.spacemit.com>
[-- Attachment #1.1: Type: text/plain, Size: 1450 bytes --]
On Wed, Feb 04, 2026 at 05:09:52PM +0800, Lv Zheng wrote:
> Add JSON HPM event aliases for SpacemiT distributed IOMMU (T100) which is
> general and compatible for all SpacemiT RISC-V SoCs.
>
> Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
> Signed-off-by: Jingyu Li <joey.li@spacemit.com>
> ---
> MAINTAINERS | 3 +
> .../arch/riscv/spacemit/iommu/sys/ioatc.json | 30 ++++
> .../arch/riscv/spacemit/iommu/sys/ioats.json | 163 ++++++++++++++++++
> 3 files changed, 196 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/riscv/spacemit/iommu/sys/ioatc.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/spacemit/iommu/sys/ioats.json
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7c50701b6001..4d91f99aa742 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -22459,12 +22459,15 @@ K: riscv
>
> RISC-V IOMMU
> M: Tomasz Jeznach <tjeznach@rivosinc.com>
> +M: Lv Zheng <lv.zheng@linux.spacemit.com>
> +M: Jingyu Li <joey.li@spacemit.com>
To be frank, this looks misguided, or at least premature, to me, given the
state of the patchset.
> L: iommu@lists.linux.dev
> L: linux-riscv@lists.infradead.org
> S: Maintained
> T: git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git
> F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> F: drivers/iommu/riscv/
> +F: tools/perf/pmu-events/arch/riscv/spacemit/iommu/
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2026-02-04 17:38 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1769562575.git.lv.zheng@spacemit.com>
2026-01-29 6:08 ` [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU Lv Zheng
2026-01-29 6:08 ` [PATCH v1.1 1/7] iommu/riscv: Enable IOMMU DMA mapping support Lv Zheng
2026-01-29 6:08 ` [PATCH v1.1 2/7] iommu/riscv: Fix WSI mode IRQ number handling Lv Zheng
2026-01-29 6:08 ` [PATCH v1.1 3/7] iommu/riscv: Add HPM support for performance monitoring Lv Zheng
2026-01-29 6:09 ` [PATCH v1.1 4/7] dt-bindings: iommu: Add spacemit/t100 features Lv Zheng
2026-01-29 10:08 ` Conor Dooley
2026-01-29 10:43 ` 郑律
2026-01-29 16:41 ` Conor Dooley
2026-01-29 17:06 ` Robin Murphy
2026-01-30 1:30 ` 郑律
2026-01-30 1:39 ` 郑律
2026-01-29 6:09 ` [PATCH v1.1 5/7] spacemit/t100: Add vendor event support for RISC-V IOMMU HPM Lv Zheng
2026-01-29 6:09 ` [PATCH v1.1 6/7] spacemit/t100: Add global filter " Lv Zheng
2026-01-29 6:09 ` [PATCH v1.1 7/7] spacemit/t100: Add SpacemiT T100 IOATC HPM support Lv Zheng
2026-02-06 10:44 ` [PATCH v1.1 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU Krzysztof Kozlowski
2026-02-04 9:08 ` [PATCH v3 0/8] " Lv Zheng
2026-02-06 10:44 ` Krzysztof Kozlowski
2026-02-07 3:41 ` Lv Zheng
2026-02-13 22:21 ` Yixun Lan
2026-02-27 5:55 ` Lv Zheng
[not found] ` <cover.1770195980.git.lv.zheng@linux.spacemit.com>
2026-02-04 9:08 ` [PATCH v3 1/8] iommu/riscv: Enable IOMMU DMA mapping support Lv Zheng
2026-02-04 9:08 ` [PATCH v3 2/8] iommu/riscv: Fix WSI mode IRQ number handling Lv Zheng
2026-02-04 17:20 ` Andrew Jones
2026-02-05 3:52 ` Lv Zheng
2026-02-05 15:04 ` Andrew Jones
2026-02-06 1:36 ` Lv Zheng
2026-02-04 9:09 ` [PATCH v3 3/8] iommu/riscv: Add HPM support for performance monitoring Lv Zheng
2026-02-04 18:39 ` Andrew Jones
2026-02-05 2:11 ` Zong Li
2026-02-05 3:35 ` Lv Zheng
2026-02-05 3:47 ` Zong Li
2026-02-05 6:11 ` Lv Zheng
2026-02-05 15:23 ` Andrew Jones
2026-02-06 3:42 ` Lv Zheng
2026-02-06 15:09 ` Andrew Jones
2026-02-07 2:11 ` Zong Li
2026-02-04 9:09 ` [PATCH v3 4/8] dt-bindings: iommu: Add spacemit/t100 features Lv Zheng
2026-02-04 17:37 ` Conor Dooley
2026-02-05 3:11 ` Lv Zheng
2026-02-05 18:24 ` Conor Dooley
2026-02-06 1:33 ` Lv Zheng
2026-02-06 10:24 ` Conor Dooley
2026-02-07 4:24 ` Lv Zheng
2026-02-07 14:55 ` Conor Dooley
2026-02-04 9:09 ` [PATCH v3 5/8] riscv/iommu: Add vendor event support for RISC-V IOMMU HPM Lv Zheng
2026-02-04 9:09 ` [PATCH v3 6/8] spacemit/t100: Add global filter awareness " Lv Zheng
2026-02-04 9:09 ` [PATCH v3 7/8] spacemit/t100: Add SpacemiT T100 IOATC HPM support Lv Zheng
2026-02-04 9:09 ` [PATCH v3 8/8] perf vendor events riscv:: Add support for spacemit,riscv-iommu HPM aliasing Lv Zheng
2026-02-04 17:38 ` Conor Dooley [this message]
2026-02-05 3:22 ` Lv Zheng
2026-02-05 9:09 ` [PATCH v4 0/7] iommu/riscv: Add HPM support for RISC-V IOMMU Lv Zheng
2026-02-06 10:46 ` Krzysztof Kozlowski
2026-02-07 3:54 ` Lv Zheng
[not found] ` <cover.1770281596.git.lv.zheng@linux.spacemit.com>
2026-02-05 9:10 ` [PATCH v4 1/7] iommu/riscv: Enable IOMMU DMA mapping support Lv Zheng
2026-02-05 9:10 ` [PATCH v4 2/7] iommu/riscv: Add HPM support for performance monitoring Lv Zheng
2026-02-05 9:10 ` [PATCH v4 3/7] dt-bindings: iommu: Add spacemit/t100 features Lv Zheng
2026-02-05 18:26 ` Conor Dooley
2026-02-06 3:44 ` Lv Zheng
2026-02-05 9:10 ` [PATCH v4 4/7] iommu/riscv: Add vendor event support for RISC-V IOMMU HPM Lv Zheng
2026-02-05 9:11 ` [PATCH v4 5/7] spacemit/t100: Add global filter awareness " Lv Zheng
2026-02-05 9:11 ` [PATCH v4 6/7] spacemit/t100: Add SpacemiT T100 IOATC HPM support Lv Zheng
2026-02-05 9:11 ` [PATCH v4 7/7] perf vendor events riscv:: Add support for spacemit,riscv-iommu HPM aliasing Lv Zheng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260204-suds-shush-d85872589cb3@spud \
--to=conor@kernel.org \
--cc=alex@ghiti.fr \
--cc=aou@eecs.berkeley.edu \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=iommu@lists.linux.dev \
--cc=joey.li@spacemit.com \
--cc=joro@8bytes.org \
--cc=krzk+dt@kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=lv.zheng@linux.spacemit.com \
--cc=palmer@dabbelt.com \
--cc=pjw@kernel.org \
--cc=robh@kernel.org \
--cc=robin.murphy@arm.com \
--cc=spacemit@lists.linux.dev \
--cc=tjeznach@rivosinc.com \
--cc=will@kernel.org \
--cc=zhijian@spacemit.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox