From: Conor Dooley <conor.dooley@microchip.com>
To: Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com>
Cc: <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<pjw@kernel.org>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<alex@ghiti.fr>, <shuah@kernel.org>
Subject: Re: [PATCH v3 1/2] riscv: Introduce support for hardware break/watchpoints
Date: Tue, 24 Feb 2026 08:03:13 +0000 [thread overview]
Message-ID: <20260224-likewise-rimless-151f6a12b092@wendy> (raw)
In-Reply-To: <CA+Ht8=aoxQp-RcFGWXXsfDyNarCn=zRhUOoG9rUCGeEw83BQvw@mail.gmail.com>
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On Tue, Feb 24, 2026 at 09:30:24AM +0530, Himanshu Chauhan wrote:
> Hi,
>
> On Mon, Feb 23, 2026 at 3:55 PM Conor Dooley <conor.dooley@microchip.com> wrote:
> >
> > On Mon, Feb 23, 2026 at 10:19:17AM +0530, Himanshu Chauhan wrote:
> > > +static void init_sbi_dbtr(void)
> > > +{
> > > + unsigned long tdata1;
> > > + struct sbiret ret;
> > > +
> > > + if (sbi_probe_extension(SBI_EXT_DBTR) <= 0) {
> > > + pr_warn("%s: SBI_EXT_DBTR is not supported\n", __func__);
> >
> > This is going to run an all systems, right? A pr_warn() seems
> > inappropriate, given that not supporting this extension isn't a problem.
> > If you want to produce warnings, only do it for < 0 return values and
> > maybe print the actual error code too?
>
> It's correct that the absence of the extension is not a problem but an
> informational message can be helpful.
> So, I can use pr_info or pr_info_once for this with proper error code. Ok?
IMO, you shouldn't be printing unless there's an actual error. If every
extension we had support for in the kernel printed a message when it was
absent, our logs would be saturated.
>
> Regards
> Himanshu
Did you miss the comment at the end about the remaining TODOs?
Cheers,
Conor.
>
> >
> > > + dbtr_total_num = 0;
> > > + goto done;
> > > + }
> > > +
> > > + ret = sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_NUM_TRIGGERS,
> > > + 0, 0, 0, 0, 0, 0);
> > > + if (ret.error) {
> > > + pr_warn("%s: Failed to detect triggers\n", __func__);
> > > + dbtr_total_num = 0;
> > > + goto done;
> > > + }
> > > +
> > > + tdata1 = 0;
> > > + tdata1 = RV_DBTR_SET_TDATA1_TYPE(tdata1, RV_DBTR_TRIG_MCONTROL6);
> > > +
> > > + ret = sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_NUM_TRIGGERS,
> > > + tdata1, 0, 0, 0, 0, 0);
> > > + if (ret.error) {
> > > + pr_warn("%s: failed to detect mcontrol6 triggers\n", __func__);
> > > + } else if (!ret.value) {
> > > + pr_warn("%s: type 6 triggers not available\n", __func__);
> > > + } else {
> > > + dbtr_total_num = ret.value;
> > > + dbtr_type = RV_DBTR_TRIG_MCONTROL6;
> > > + pr_warn("%s: mcontrol6 trigger available.\n", __func__);
> > > + goto done;
> > > + }
> > > +
> > > + /* fallback to type 2 triggers if type 6 is not available */
> > > +
> > > + tdata1 = 0;
> > > + tdata1 = RV_DBTR_SET_TDATA1_TYPE(tdata1, RV_DBTR_TRIG_MCONTROL);
> > > +
> > > + ret = sbi_ecall(SBI_EXT_DBTR, SBI_EXT_DBTR_NUM_TRIGGERS,
> > > + tdata1, 0, 0, 0, 0, 0);
> > > + if (ret.error) {
> > > + pr_warn("%s: failed to detect mcontrol triggers\n", __func__);
> > > + } else if (!ret.value) {
> > > + pr_warn("%s: type 2 triggers not available\n", __func__);
> > > + } else {
> > > + dbtr_total_num = ret.value;
> > > + dbtr_type = RV_DBTR_TRIG_MCONTROL;
> > > + goto done;
> > > + }
> > > +
> > > +done:
> > > + dbtr_init = 1;
> > > +}
> >
> > > +
> > > +void hw_breakpoint_pmu_read(struct perf_event *bp)
> > > +{
> > > + /* TODO */
> > > +}
> > > +
> > > +void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
> > > +{
> > > + /* TODO */
> > > +}
> > > +
> > > +void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
> > > +{
> > > + /* TODO */
> > > +}
> >
> > This isn't an RFC, why does it have TODOs?
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next prev parent reply other threads:[~2026-02-24 8:04 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-23 4:49 [PATCH v3 0/2] riscv: Introduce support for hardware break/watchpoints Himanshu Chauhan
2026-02-23 4:49 ` [PATCH v3 1/2] " Himanshu Chauhan
2026-02-23 10:24 ` Conor Dooley
2026-02-24 4:00 ` Himanshu Chauhan
2026-02-24 8:03 ` Conor Dooley [this message]
2026-02-25 5:03 ` Himanshu Chauhan
2026-02-25 9:00 ` Conor Dooley
2026-02-26 2:47 ` Himanshu Chauhan
2026-02-26 8:48 ` Conor Dooley
2026-02-26 5:35 ` Anup Patel
2026-02-26 8:44 ` Conor Dooley
2026-02-26 11:40 ` Anup Patel
2026-02-26 12:35 ` Conor Dooley
2026-02-26 13:03 ` Anup Patel
2026-02-26 8:52 ` Conor Dooley
2026-03-18 12:00 ` Ilya Mamay
2026-04-06 4:51 ` Himanshu Chauhan
2026-04-07 10:29 ` Ilya Mamay
2026-04-07 15:22 ` Himanshu Chauhan
2026-03-19 10:36 ` Ilya Mamay
2026-04-06 4:49 ` Himanshu Chauhan
2026-04-07 11:34 ` Ilya Mamay
2026-04-07 15:29 ` Himanshu Chauhan
2026-04-03 7:37 ` liangzhen
2026-04-06 4:48 ` Himanshu Chauhan
2026-04-07 1:47 ` liangzhen
2026-04-07 4:53 ` Himanshu Chauhan
2026-04-07 10:32 ` liangzhen
2026-02-23 4:49 ` [PATCH v3 2/2] riscv: Add breakpoint and watchpoint test for riscv Himanshu Chauhan
2026-04-21 12:00 ` Ilya Mamay
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