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From: Ilya Mamay <mmamayka01@gmail.com>
To: Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, shuah@kernel.org
Subject: Re: [PATCH v3 1/2] riscv: Introduce support for hardware break/watchpoints
Date: Tue, 7 Apr 2026 13:29:49 +0300	[thread overview]
Message-ID: <20260407102949.yjsihtpgkau6fndl@imamay-pc> (raw)
In-Reply-To: <CA+Ht8=ZDH+o9ocgDpX+JQ0TQONYn_eVRiEGedeauUoa4tsK6nw@mail.gmail.com>

Hi, Himanshu

Thanks for your reply. However, could you please explain the actual purpose of
this ecall_lock? I still don't understand why it is needed.

On Mon, Apr 06, 2026 at 10:21:06AM +0530, Himanshu Chauhan wrote:
> Hi,
> 
> On Wed, Mar 18, 2026 at 5:30 PM Ilya Mamay <mmamayka01@gmail.com> wrote:
> >
> > Hi,
> >
> > Thank you for this patch - it;s a valuable addition to the RISC-V HBP support.
> > I have one question regarding the locking:
> >
> > On Mon, Feb 23, 2026 at 10:19:17AM +0530, Himanshu Chauhan wrote:
> > > +int arch_install_hw_breakpoint(struct perf_event *event)
> > > +{
> > > +     struct arch_hw_breakpoint *bp = counter_arch_bp(event);
> > > +     union sbi_dbtr_shmem_entry *shmem = this_cpu_ptr(sbi_dbtr_shmem);
> > > +     struct sbi_dbtr_data_msg *xmit;
> > > +     struct sbi_dbtr_id_msg *recv;
> > > +     struct perf_event **slot;
> > > +     unsigned long idx;
> > > +     struct sbiret ret;
> > > +     int err = 0;
> > > +
> > > +     raw_spin_lock_irqsave(this_cpu_ptr(&ecall_lock),
> > > +                           *this_cpu_ptr(&ecall_lock_flags));
> >
> > Could you clarify the purpose of the ecall_lock in arch_install_hw_breakpoint and
> > arch_update_hw_breakpoint? Why is it used only in two functions mentioned above,
> > but not in other PMU callbacks like arch_uninstall_hw_breakpoint?
> >
> I probably missed it in arch_uninstall_hw_breakpoint. I will take care of it.
> 
> Thanks & Regards
> Himanshu
> 
> > Regards
> > Ilya
> >
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv

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  reply	other threads:[~2026-04-07 10:30 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-23  4:49 [PATCH v3 0/2] riscv: Introduce support for hardware break/watchpoints Himanshu Chauhan
2026-02-23  4:49 ` [PATCH v3 1/2] " Himanshu Chauhan
2026-02-23 10:24   ` Conor Dooley
2026-02-24  4:00     ` Himanshu Chauhan
2026-02-24  8:03       ` Conor Dooley
2026-02-25  5:03         ` Himanshu Chauhan
2026-02-25  9:00           ` Conor Dooley
2026-02-26  2:47             ` Himanshu Chauhan
2026-02-26  8:48               ` Conor Dooley
2026-02-26  5:35             ` Anup Patel
2026-02-26  8:44               ` Conor Dooley
2026-02-26 11:40                 ` Anup Patel
2026-02-26 12:35                   ` Conor Dooley
2026-02-26 13:03                     ` Anup Patel
2026-02-26  8:52   ` Conor Dooley
2026-03-18 12:00   ` Ilya Mamay
2026-04-06  4:51     ` Himanshu Chauhan
2026-04-07 10:29       ` Ilya Mamay [this message]
2026-04-07 15:22         ` Himanshu Chauhan
2026-03-19 10:36   ` Ilya Mamay
2026-04-06  4:49     ` Himanshu Chauhan
2026-04-07 11:34       ` Ilya Mamay
2026-04-07 15:29         ` Himanshu Chauhan
2026-04-03  7:37   ` liangzhen
2026-04-06  4:48     ` Himanshu Chauhan
2026-04-07  1:47       ` liangzhen
2026-04-07  4:53         ` Himanshu Chauhan
2026-04-07 10:32           ` liangzhen
2026-02-23  4:49 ` [PATCH v3 2/2] riscv: Add breakpoint and watchpoint test for riscv Himanshu Chauhan
2026-04-21 12:00   ` Ilya Mamay

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