From: Conor Dooley <conor@kernel.org>
To: Bo Gan <ganboing@gmail.com>
Cc: linux-riscv@lists.infradead.org, samuel.holland@sifive.com,
david@redhat.com, palmer@dabbelt.com, pjw@kernel.org,
gaohan@iscas.ac.cn, me@ziyao.cc, lizhi2@eswincomputing.com,
hal.feng@starfivetech.com, marcel@ziswiler.com, kernel@esmil.dk,
devicetree@vger.kernel.org
Subject: Re: [RFC PATCH 1/6] riscv: Add a custom, simplified version of Svpbmt "XPbmtUC"
Date: Sat, 14 Mar 2026 12:17:12 +0000 [thread overview]
Message-ID: <20260314-subdued-morally-f20a84fd446c@spud> (raw)
In-Reply-To: <9592ecf2-8410-4df7-9b2c-17564426240d@gmail.com>
[-- Attachment #1.1: Type: text/plain, Size: 1984 bytes --]
On Fri, Mar 13, 2026 at 10:06:42PM -0700, Bo Gan wrote:
> > To be honest, I'm not completely dead-set opposed to a property that has
> > the bit positioning, but any property being added for what is
> > effectively an erratum needs to pass a high bar when the info could be
> > gathered in another way. That the eic7700 one depends on firmware for
> > what the bit may be is points in your favour, since firmware variability
> > is part of what dt is there to do. The jh7110 is points against, since
> > it could be fished out of the errata handling code.
> >
> Even for JH7110, I don't think it can be handled through the errata. It
> describes the errata of the core (if I'm not mistaken), and there can be
> other SoCs using the same core with the same archid/impid, but maps the
> peripherals differently, and the UC bit position doesn't apply there. I
> think you are probably looking for "SoC level errata" handling. It's not
> there AFAIK. Hence I guess both SoC cases point in favor of the dt prop?
I dunno, nothing wrong with checking the devicetree during the errata
"probe" code. Checks are not limited to imp/arch ids, can do ecalls etc
etc in there too, so looking at the root compatible would be possible.
Either way, if people like what you've done here generally (because
coming up with our own use of PTE bits could be controversial), and a
custom property of some sort is to be used, you need to provide a good
justification of why it is needed in the commit messages because you're
setting a precedent of being the first "extension" conjured up to suit
linux that would need that kind of functionality.
Need to demonstrate that it describes an aspect of the hardware, and
isn't being conjured up to configure software to use one out of several
possible values, that it may even be able to determine heuristically
from information already provided in the devicetree (like the root
compatible or a completely described memory node).
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2026-03-14 12:17 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-13 8:44 [RFC PATCH 0/6] riscv: support EIC770X/JH7110 noncoherent devices with XPbmtUC Bo Gan
2026-03-13 8:44 ` [RFC PATCH 1/6] riscv: Add a custom, simplified version of Svpbmt "XPbmtUC" Bo Gan
2026-03-13 13:24 ` Conor Dooley
2026-03-13 21:33 ` Bo Gan
2026-03-13 23:55 ` Conor Dooley
2026-03-14 0:29 ` Bo Gan
2026-03-14 1:18 ` Conor Dooley
2026-03-14 5:06 ` Bo Gan
2026-03-14 12:17 ` Conor Dooley [this message]
2026-03-16 21:22 ` Bo Gan
2026-03-15 12:05 ` Conor Dooley
2026-03-13 8:44 ` [RFC PATCH 2/6] riscv: alternatives: support auipc+load pair Bo Gan
2026-03-13 8:44 ` [RFC PATCH 3/6] riscv: apply page table attribute bits for XPbmtUC Bo Gan
2026-03-13 13:24 ` Conor Dooley
2026-03-13 21:34 ` Bo Gan
2026-03-13 8:44 ` [RFC PATCH 4/6] riscv: select RISCV_ISA_XPBMTUC in STARFIVE and ESWIN SoC Bo Gan
2026-03-13 13:28 ` Conor Dooley
2026-03-13 21:35 ` Bo Gan
2026-03-13 8:44 ` [RFC PATCH 5/6] riscv: dts: starfive: jh7110: activate XPbmtUC Bo Gan
2026-03-13 13:48 ` Conor Dooley
2026-03-13 21:59 ` Bo Gan
2026-03-13 23:46 ` Conor Dooley
2026-03-13 8:44 ` [RFC PATCH 6/6] [TESTING-ONLY] riscv: dts: eswin: eic7700: " Bo Gan
2026-03-13 12:30 ` [RFC PATCH 0/6] riscv: support EIC770X/JH7110 noncoherent devices with XPbmtUC Conor Dooley
2026-03-13 22:17 ` Bo Gan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260314-subdued-morally-f20a84fd446c@spud \
--to=conor@kernel.org \
--cc=david@redhat.com \
--cc=devicetree@vger.kernel.org \
--cc=ganboing@gmail.com \
--cc=gaohan@iscas.ac.cn \
--cc=hal.feng@starfivetech.com \
--cc=kernel@esmil.dk \
--cc=linux-riscv@lists.infradead.org \
--cc=lizhi2@eswincomputing.com \
--cc=marcel@ziswiler.com \
--cc=me@ziyao.cc \
--cc=palmer@dabbelt.com \
--cc=pjw@kernel.org \
--cc=samuel.holland@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox