Re: [RFC PATCH 3/6] riscv: apply page table attribute bits for XPbmtUC

From: Bo Gan <ganboing@gmail.com>
To: Conor Dooley <conor@kernel.org>, Bo Gan <ganboing@gmail.com>
Cc: linux-riscv@lists.infradead.org, samuel.holland@sifive.com,
	david@redhat.com, palmer@dabbelt.com, pjw@kernel.org,
	gaohan@iscas.ac.cn, me@ziyao.cc, lizhi2@eswincomputing.com,
	hal.feng@starfivetech.com, marcel@ziswiler.com, kernel@esmil.dk,
	devicetree@vger.kernel.org
Subject: Re: [RFC PATCH 3/6] riscv: apply page table attribute bits for XPbmtUC
Date: Fri, 13 Mar 2026 14:34:27 -0700	[thread overview]
Message-ID: <31b0abc4-b107-4c95-b6c8-51941330b0f4@gmail.com> (raw)
In-Reply-To: <20260313-breezy-from-6b5ad9e9a5ac@spud>

Hi Conor,

On 3/13/26 06:24, Conor Dooley wrote:
> On Fri, Mar 13, 2026 at 01:44:04AM -0700, Bo Gan wrote:
>> Apply the UC bit like Svpbmt and THEAD_MAE does. Also changed the
>> _PAGE_PFN_MASK definition to exclude the UC bit, as it's position
>> is now determined at runtime, and can be part of PPN.
>>
>> Signed-off-by: Bo Gan <ganboing@gmail.com>
> 
> This should be squashed with the patch adding detection and the Kconfig
> option.
> 

Sure.

>> ---
>>   arch/riscv/include/asm/errata_list.h | 17 +++++++++++++++--
>>   arch/riscv/include/asm/pgtable-64.h  |  9 ++++++++-
>>   2 files changed, 23 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
>> index 6694b5ccdcf85..ba0f3d4dd0cbb 100644
>> --- a/arch/riscv/include/asm/errata_list.h
>> +++ b/arch/riscv/include/asm/errata_list.h
>> @@ -53,6 +53,16 @@ asm(ALTERNATIVE(	\
>>   	: /* no inputs */	\
>>   	: "memory")
>>   
>> +#ifdef CONFIG_64BIT
>> +#define ALT_PAGE_CUST_BIT(_bit)						\
>> +asm(ALTERNATIVE("li %0, 0\t\nnop",					\
>> +		"1: auipc %0, %%pcrel_hi(riscv_xpbmtuc_mask)\t\n"	\
>> +		      "ld %0, %%pcrel_lo(1b)(%0)", 0,			\
>> +			RISCV_ISA_EXT_XPBMTUC,				\
>> +			CONFIG_RISCV_ISA_XPBMTUC)			\
>> +		: "=r"(_bit))
>> +#endif
>> +
>>   /*
>>    * _val is marked as "will be overwritten", so need to set it to 0
>>    * in the default case.
>> @@ -60,11 +70,14 @@ asm(ALTERNATIVE(	\
>>   #define ALT_SVPBMT_SHIFT 61
>>   #define ALT_THEAD_MAE_SHIFT 59
>>   #define ALT_SVPBMT(_val, prot)						\
>> -asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
>> +asm(ALTERNATIVE_3("li %0, 0\t\nnop",					\
>>   		  "li %0, %1\t\nslli %0,%0,%3", 0,			\
>>   			RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,	\
>>   		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,	\
>> -			ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE)	\
>> +			ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE,	\
>> +		  "1: auipc %0, %%pcrel_hi(riscv_xpbmtuc_mask)\t\n"	\
>> +			"ld %0, %%pcrel_lo(1b)(%0)", 0,			\
>> +			RISCV_ISA_EXT_XPBMTUC, XPBMTUC_HAS##prot)	\
>>   		: "=r"(_val)						\
>>   		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
>>   		  "I"(prot##_THEAD >> ALT_THEAD_MAE_SHIFT),		\
>> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
>> index 1a6d04884111d..aab6990d92238 100644
>> --- a/arch/riscv/include/asm/pgtable-64.h
>> +++ b/arch/riscv/include/asm/pgtable-64.h
>> @@ -76,7 +76,14 @@ typedef struct {
>>    * | 63 | 62 61 | 60 54 | 53  10 | 9             8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
>>    *   N      MT     RSV    PFN      reserved for SW   D   A   G   U   X   W   R   V
>>    */
>> -#define _PAGE_PFN_MASK  GENMASK(53, 10)
>> +static inline u64 riscv_pfn_mask(void)
>> +{
>> +	u64 cust_bit;
>> +
>> +	ALT_PAGE_CUST_BIT(cust_bit);
>> +	return GENMASK(53, 10) ^ cust_bit;
>> +}
>> +#define _PAGE_PFN_MASK  riscv_pfn_mask()
>>   
>>   /*
>>    * [63] Svnapot definitions:
>> -- 
>> 2.34.1
>>

Bo

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