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From: Conor Dooley <conor@kernel.org>
To: broonie@kernel.org
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Cyril Jean <cyril.jean@microchip.com>,
	Valentina.FernandezAlanis@microchip.com,
	linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org,
	linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: [PATCH v1 2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations
Date: Wed, 22 Apr 2026 16:15:43 +0100	[thread overview]
Message-ID: <20260422-omit-fancy-ad0bac3d843d@spud> (raw)
In-Reply-To: <20260422-foe-strength-a5d8ad650ef4@spud>

From: Conor Dooley <conor.dooley@microchip.com>

The core will deal with reads by creating clock cycles itself, there's
no need to generate clock cycles by transmitting garbage data at the
driver level. Further, transmitting garbage data just bricks the transfer
since QSPI doesn't have a dedicated master-out line like MOSI in regular
SPI. I'm not entirely sure if the transfer is bricked because of the
garbage data being transmitted on the bus or because the core loses
track of whether it is supposed to be sending or receiving data.

Fixes: 8f9cf02c88528 ("spi: microchip-core-qspi: Add regular transfers")
CC: stable@vger.kernel.org
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/spi/spi-microchip-core-qspi.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microchip-core-qspi.c
index 0a161727706ef..d39b04f9b6b38 100644
--- a/drivers/spi/spi-microchip-core-qspi.c
+++ b/drivers/spi/spi-microchip-core-qspi.c
@@ -693,18 +693,28 @@ static int mchp_coreqspi_transfer_one(struct spi_controller *ctlr, struct spi_de
 				      struct spi_transfer *t)
 {
 	struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
+	bool dual_quad = false;
 
 	qspi->tx_len = t->len;
 
+	if (t->tx_nbits == SPI_NBITS_QUAD || t->rx_nbits == SPI_NBITS_QUAD ||
+			t->tx_nbits == SPI_NBITS_DUAL ||
+			t->rx_nbits == SPI_NBITS_DUAL)
+		dual_quad = true;
+
 	if (t->tx_buf)
 		qspi->txbuf = (u8 *)t->tx_buf;
 
 	if (!t->rx_buf) {
 		mchp_coreqspi_write_op(qspi);
-	} else {
+	} else if (!dual_quad) {
 		qspi->rxbuf = (u8 *)t->rx_buf;
 		qspi->rx_len = t->len;
 		mchp_coreqspi_write_read_op(qspi);
+	} else {
+		qspi->rxbuf = (u8 *)t->rx_buf;
+		qspi->rx_len = t->len;
+		mchp_coreqspi_read_op(qspi);
 	}
 
 	return 0;
-- 
2.53.0


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  parent reply	other threads:[~2026-04-22 15:17 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-22 15:15 [PATCH v1 0/5] microchip core-qspi gpio-cs fixes + cleanup Conor Dooley
2026-04-22 15:15 ` [PATCH v1 1/5] spi: microchip-core-qspi: control built-in cs manually Conor Dooley
2026-04-22 15:15 ` Conor Dooley [this message]
2026-04-22 15:15 ` [PATCH v1 3/5] spi: microchip-core-qspi: report device on which timeout occured instead of which controller Conor Dooley
2026-04-22 15:15 ` [PATCH v1 4/5] spi: microchip-core-qspi: remove an unused define Conor Dooley
2026-04-22 15:15 ` [PATCH v1 5/5] spi: microchip-core-qspi: remove some inline markings Conor Dooley
2026-04-22 15:25 ` [PATCH v1 0/5] microchip core-qspi gpio-cs fixes + cleanup Mark Brown
2026-04-22 16:12   ` Conor Dooley

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