From: fangyu.yu@linux.alibaba.com
To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca,
kevin.tian@intel.com, baolu.lu@linux.intel.com,
vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev,
skhawaja@google.com, jgg@nvidia.com
Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com,
kvm@vger.kernel.org, iommu@lists.linux.dev,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Fangyu Yu <fangyu.yu@linux.alibaba.com>
Subject: [RFC PATCH v2 10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries
Date: Thu, 7 May 2026 19:37:06 +0800 [thread overview]
Message-ID: <20260507113706.11400-11-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com>
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Previously, only IOTINVAL.VMA was issued, which is insufficient for
second-stage address translation consistency.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
drivers/iommu/riscv/iommu.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index b7944149dcfe..44dd268cc3ce 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -1065,12 +1065,15 @@ static void riscv_iommu_iodir_iotinval(struct riscv_iommu_device *iommu,
/*
* else: IOTINVAL.VMA with GV=1,AV=PSCV=0,and
* GSCID=DC.iohgatp.GSCID
- *
+ */
+ riscv_iommu_cmd_send(iommu, &cmd);
+ /*
* IOTINVAL.GVMA with GV=1,AV=0,and
* GSCID=DC.iohgatp.GSCID
- * TODO: For now, the Second-Stage feature have not yet been merged,
- * also issue IOTINVAL.GVMA once second-stage support is merged.
*/
+ riscv_iommu_cmd_inval_gvma(&cmd);
+ riscv_iommu_cmd_inval_set_gscid(&cmd,
+ FIELD_GET(RISCV_IOMMU_DC_IOHGATP_GSCID, iohgatp));
}
riscv_iommu_cmd_send(iommu, &cmd);
}
--
2.50.1
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prev parent reply other threads:[~2026-05-07 11:37 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-07 11:36 [RFC PATCH v2 00/10] iommu/riscv: Add hardware dirty tracking for second-stage domains fangyu.yu
2026-05-07 11:36 ` [RFC PATCH v2 01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-05-07 11:36 ` [RFC PATCH v2 02/10] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-05-07 11:36 ` [RFC PATCH v2 03/10] iommu/riscv: report iommu capabilities fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 04/10] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 05/10] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 08/10] iommu/riscv: Pre-enable GADE for second-stage domains fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 09/10] iommu/riscv: Add dirty tracking support " fangyu.yu
2026-05-07 11:37 ` fangyu.yu [this message]
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