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From: fangyu.yu@linux.alibaba.com
To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca,
	kevin.tian@intel.com, baolu.lu@linux.intel.com,
	vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev,
	skhawaja@google.com, jgg@nvidia.com
Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com,
	kvm@vger.kernel.org, iommu@lists.linux.dev,
	kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Fangyu Yu <fangyu.yu@linux.alibaba.com>
Subject: [RFC PATCH v2 08/10] iommu/riscv: Pre-enable GADE for second-stage domains
Date: Thu,  7 May 2026 19:37:04 +0800	[thread overview]
Message-ID: <20260507113706.11400-9-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com>

From: Fangyu Yu <fangyu.yu@linux.alibaba.com>

Pre-enable RISCV_IOMMU_DC_TC_GADE in the device context when
attaching a second-stage domain, if the IOMMU supports AMO_HWAD.

Software pre-populates second-stage page tables with D set, so
enabling GADE by default does not change normal behavior. When
dirty tracking is enabled, iommufd clears the pre-set D bits and
GADE becomes necessary for hardware to update the dirty bit on
write access.

This avoids toggling GADE dynamically and keeps device context
setup consistent with second-stage domain attachment.

Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
 drivers/iommu/riscv/iommu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index ebf42f74e194..4adf2b6be89b 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -1229,6 +1229,8 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,
 		dc.iohgatp = FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) |
 			     FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) |
 			     FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn);
+		if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD)
+			dc.tc |= RISCV_IOMMU_DC_TC_GADE;
 	} else {
 		dc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) |
 		      FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn);
-- 
2.50.1


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  parent reply	other threads:[~2026-05-07 11:37 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-07 11:36 [RFC PATCH v2 00/10] iommu/riscv: Add hardware dirty tracking for second-stage domains fangyu.yu
2026-05-07 11:36 ` [RFC PATCH v2 01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-05-07 11:36 ` [RFC PATCH v2 02/10] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-05-07 11:36 ` [RFC PATCH v2 03/10] iommu/riscv: report iommu capabilities fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 04/10] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 05/10] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-05-07 11:37 ` fangyu.yu [this message]
2026-05-07 11:37 ` [RFC PATCH v2 09/10] iommu/riscv: Add dirty tracking support for second-stage domains fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries fangyu.yu

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