* [PATCH 1/2] riscv: dts: spacemit: k3: add USB controller and USB phy support
2026-07-09 4:04 [PATCH 0/2] riscv: dts: spacemit: k3: Add USB/PCIe devices Inochi Amaoto
@ 2026-07-09 4:04 ` Inochi Amaoto
2026-07-09 4:04 ` [PATCH 2/2] riscv: dts: spacemit: k3: Add PCIe device node Inochi Amaoto
1 sibling, 0 replies; 3+ messages in thread
From: Inochi Amaoto @ 2026-07-09 4:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan
Cc: Inochi Amaoto, devicetree, linux-riscv, spacemit, linux-kernel,
Yixun Lan, Longbin Li
Add all USB device node to the Spacemit K3.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++
arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++
2 files changed, 55 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index b89c1521e664..2a6d35a64d5c 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -182,6 +182,11 @@ dldo7: dldo7 {
};
};
+&combophy {
+ spacemit,apmu = <&syscon_apmu 0x11>;
+ status = "okay";
+};
+
ð0 {
pinctrl-names = "default";
pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>;
@@ -221,3 +226,11 @@ hub@1 {
&usb2_phy {
status = "okay";
};
+
+&usb3d_u2phy {
+ status = "okay";
+};
+
+&usb3d {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 19fc9b49668e..82c9e2da82e9 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/spacemit,k3-clocks.h>
#include <dt-bindings/reset/spacemit,k3-resets.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
/dts-v1/;
@@ -438,6 +439,47 @@ soc: soc {
dma-noncoherent;
ranges;
+ usb3d: usb@81a00000 {
+ compatible = "spacemit,k3-dwc3";
+ reg = <0x0 0x81a00000 0x0 0x10000>;
+ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&saplic>;
+ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>;
+ clock-names = "usbdrd30";
+ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>,
+ <&syscon_apmu RESET_APMU_USB3_D_VCC>,
+ <&syscon_apmu RESET_APMU_USB3_D_PHY>;
+ reset-names = "ahb", "vcc", "phy";
+ phys = <&usb3d_u2phy>,
+ <&combophy 4 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi";
+ snps,dis_enblslpm_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,parkmode-disable-ss-quirk;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ usb3d_u2phy: phy@81b00000 {
+ compatible = "spacemit,k3-usb2-phy";
+ reg = <0x0 0x81b00000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ combophy: phy@81d00000 {
+ compatible = "spacemit,k3-combo-phy";
+ reg = <0x0 0x81d00000 0x0 0x600000>;
+ #phy-cells = <2>;
+ spacemit,apb-spare = <&pll>;
+ status = "disabled";
+ };
+
usb2_host: usb@c0a00000 {
compatible = "spacemit,k3-dwc3";
reg = <0x0 0xc0a00000 0x0 0x10000>;
--
2.55.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH 2/2] riscv: dts: spacemit: k3: Add PCIe device node
2026-07-09 4:04 [PATCH 0/2] riscv: dts: spacemit: k3: Add USB/PCIe devices Inochi Amaoto
2026-07-09 4:04 ` [PATCH 1/2] riscv: dts: spacemit: k3: add USB controller and USB phy support Inochi Amaoto
@ 2026-07-09 4:04 ` Inochi Amaoto
1 sibling, 0 replies; 3+ messages in thread
From: Inochi Amaoto @ 2026-07-09 4:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan
Cc: Inochi Amaoto, devicetree, linux-riscv, spacemit, linux-kernel,
Yixun Lan, Longbin Li
Add all PCIe device node for Spacemit K3.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 38 ++++
arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++
arch/riscv/boot/dts/spacemit/k3.dtsi | 195 +++++++++++++++++++
3 files changed, 266 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index 2a6d35a64d5c..1eb5abbc61f9 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -205,6 +205,44 @@ phy0: phy@1 {
};
};
+&pcie0_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_0_cfg>;
+ num-lanes = <4>;
+ status = "okay";
+
+ pcie@0 {
+ vpcie3v3-supply = <®_aux_vcc3v3>;
+ phys = <&combophy 0 PHY_TYPE_PCIE>,
+ <&combophy 1 PHY_TYPE_PCIE>;
+ };
+};
+
+&pcie2_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_0_cfg>;
+ num-lanes = <2>;
+ status = "okay";
+
+ pcie@0 {
+ vpcie3v3-supply = <®_aux_vcc3v3>;
+ phys = <&combophy 2 PHY_TYPE_PCIE>,
+ <&combophy 3 PHY_TYPE_PCIE>;
+ };
+};
+
+&pcie4_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie4_0_cfg>;
+ num-lanes = <1>;
+ status = "okay";
+
+ pcie@0 {
+ vpcie3v3-supply = <®_aux_vcc3v3>;
+ phys = <&combophy 5 PHY_TYPE_PCIE>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_0_cfg>;
diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
index 3ee1471f3798..68aa21a5279f 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
@@ -689,4 +689,37 @@ uart0-0-pins {
drive-strength = <25>;
};
};
+
+ pcie0_0_cfg: pcie0-0-cfg {
+ pcie0-0-pins {
+ pinmux = <K3_PADCONF(79, 5)>, /* pcie0 perst */
+ <K3_PADCONF(81, 5)>; /* pcie0 clkreq */
+
+ bias-pull-up = <1>;
+ drive-strength = <33>;
+ power-source = <1800>;
+ };
+ };
+
+ pcie2_0_cfg: pcie2-0-cfg {
+ pcie2-0-pins {
+ pinmux = <K3_PADCONF(25, 4)>, /* pcie2 perst */
+ <K3_PADCONF(27, 4)>; /* pcie2 clkreq */
+
+ drive-strength = <38>;
+ power-source = <3300>;
+ };
+ };
+
+ pcie4_0_cfg: pcie4-0-cfg {
+ pcie4-0-pins {
+ pinmux = <K3_PADCONF(76, 5)>, /* pcie4 perst */
+ <K3_PADCONF(77, 5)>, /* pcie4 wake */
+ <K3_PADCONF(78, 5)>; /* pcie4 clkreq */
+
+ bias-pull-up = <1>;
+ drive-strength = <33>;
+ power-source = <1800>;
+ };
+ };
};
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 82c9e2da82e9..53cfb2ad48cf 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -439,6 +439,201 @@ soc: soc {
dma-noncoherent;
ranges;
+ pcie0_rc: pcie@80000000 {
+ compatible = "spacemit,k3-pcie";
+ reg = <0x0 0x80000000 0x0 0x00001000>,
+ <0x0 0x80300000 0x0 0x00003f20>,
+ <0x11 0x00000000 0x0 0x00010000>,
+ <0x0 0x82900000 0x0 0x00001000>,
+ <0x0 0x80100000 0x0 0x00001000>;
+ reg-names = "dbi", "atu", "config", "link", "dbi2";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>,
+ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>,
+ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>;
+ clock-names = "dbi", "mstr", "slv";
+ msi-parent = <&simsic>;
+ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>,
+ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>,
+ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>;
+ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>,
+ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>,
+ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>;
+ reset-names = "dbi", "mstr", "slv";
+ max-link-speed = <3>;
+ linux,pci-domain = <0>;
+ spacemit,apmu = <&syscon_apmu 0x1f0>;
+ status = "disabled";
+
+ pcie0_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie1_rc: pcie@80400000 {
+ compatible = "spacemit,k3-pcie";
+ reg = <0x0 0x80400000 0x0 0x00001000>,
+ <0x0 0x80700000 0x0 0x00003f20>,
+ <0x11 0x80000000 0x0 0x00010000>,
+ <0x0 0x82c00000 0x0 0x00001000>,
+ <0x0 0x80500000 0x0 0x00001000>;
+ reg-names = "dbi", "atu", "config", "link", "dbi2";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>,
+ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>,
+ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>;
+ clock-names = "dbi", "mstr", "slv";
+ msi-parent = <&simsic>;
+ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>,
+ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>,
+ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>;
+ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>,
+ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>,
+ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>;
+ reset-names = "dbi", "mstr", "slv";
+ max-link-speed = <3>;
+ linux,pci-domain = <1>;
+ spacemit,apmu = <&syscon_apmu 0x1d0>;
+ status = "disabled";
+
+ pcie1_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie2_rc: pcie@80800000 {
+ compatible = "spacemit,k3-pcie";
+ reg = <0x0 0x80800000 0x0 0x00001000>,
+ <0x0 0x80b00000 0x0 0x00003f20>,
+ <0x12 0x00000000 0x0 0x00010000>,
+ <0x0 0x82d00000 0x0 0x00001000>,
+ <0x0 0x80900000 0x0 0x00001000>;
+ reg-names = "dbi", "atu", "config", "link", "dbi2";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>,
+ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>,
+ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>;
+ clock-names = "dbi", "mstr", "slv";
+ msi-parent = <&simsic>;
+ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>,
+ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>,
+ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>;
+ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>,
+ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>,
+ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>;
+ reset-names = "dbi", "mstr", "slv";
+ linux,pci-domain = <2>;
+ max-link-speed = <3>;
+ spacemit,apmu = <&syscon_apmu 0x1c8>;
+ status = "disabled";
+
+ pcie2_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie3_rc: pcie@80c00000 {
+ compatible = "spacemit,k3-pcie";
+ reg = <0x0 0x80c00000 0x0 0x00001000>,
+ <0x0 0x80f00000 0x0 0x00003f20>,
+ <0x12 0x80000000 0x0 0x00010000>,
+ <0x0 0x82a00000 0x0 0x00001000>,
+ <0x0 0x80d00000 0x0 0x00001000>;
+ reg-names = "dbi", "atu", "config", "link", "dbi2";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>,
+ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>,
+ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>;
+ clock-names = "dbi", "mstr", "slv";
+ msi-parent = <&simsic>;
+ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>,
+ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>,
+ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>;
+ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>,
+ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>,
+ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>;
+ reset-names = "dbi", "mstr", "slv";
+ linux,pci-domain = <3>;
+ bus-range = <0x00 0xff>;
+ max-link-speed = <3>;
+ spacemit,apmu = <&syscon_apmu 0x1e0>;
+ status = "disabled";
+
+ pcie3_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie4_rc: pcie@81000000 {
+ compatible = "spacemit,k3-pcie";
+ reg = <0x0 0x81000000 0x0 0x00001000>,
+ <0x0 0x81300000 0x0 0x00003f20>,
+ <0x12 0xc0000000 0x0 0x00010000>,
+ <0x0 0x82b00000 0x0 0x00001000>,
+ <0x0 0x81100000 0x0 0x00001000>;
+ reg-names = "dbi", "atu", "config", "link", "dbi2";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>,
+ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>,
+ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>;
+ clock-names = "dbi", "mstr", "slv";
+ msi-parent = <&simsic>;
+ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>,
+ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>,
+ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>;
+ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>,
+ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>,
+ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>;
+ reset-names = "dbi", "mstr", "slv";
+ linux,pci-domain = <4>;
+ max-link-speed = <3>;
+ spacemit,apmu = <&syscon_apmu 0x1e8>;
+ status = "disabled";
+
+ pcie4_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
usb3d: usb@81a00000 {
compatible = "spacemit,k3-dwc3";
reg = <0x0 0x81a00000 0x0 0x10000>;
--
2.55.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 3+ messages in thread