From: Paul Walmsley <pjw@kernel.org>
To: "Christian König" <christian.koenig@amd.com>
Cc: Matthew Brost <matthew.brost@intel.com>,
Simona Vetter <simona@ffwll.ch>, Yao Zi <ziyao@disroot.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Vivian Wang <wangruikang@iscas.ac.cn>,
dri-devel@lists.freedesktop.org, Han Gao <rabenda.cn@gmail.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
linux-kernel@vger.kernel.org, Maxime Ripard <mripard@kernel.org>,
Huang Rui <ray.huang@amd.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Matthew Auld <matthew.auld@intel.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, David Airlie <airlied@gmail.com>,
Inochi Amaoto <inochiama@gmail.com>
Subject: Re: [PATCH v2] drm/ttm: add pgprot handling for RISC-V
Date: Mon, 27 Oct 2025 10:41:01 -0600 (MDT) [thread overview]
Message-ID: <5fed2297-4e51-6aa9-464a-6f8a2cf8fcc6@kernel.org> (raw)
In-Reply-To: <dff6216d-b4a4-4d5d-89e3-e393dc018dec@amd.com>
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On Mon, 27 Oct 2025, Christian König wrote:
> On 10/20/25 07:35, Icenowy Zheng wrote:
> > The RISC-V Svpbmt privileged extension provides support for overriding
> > page memory coherency attributes, and, along with vendor extensions like
> > Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
> >
> > Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
> > and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
> > access attributes.
[ ... ]
> > diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
> > index b3fffe7b5062a..aa137ead5cc59 100644
> > --- a/drivers/gpu/drm/ttm/ttm_module.c
> > +++ b/drivers/gpu/drm/ttm/ttm_module.c
> > @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
> > #endif /* CONFIG_UML */
> > #endif /* __i386__ || __x86_64__ */
> > #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
> > - defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
> > + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
> > + defined(__riscv)
>
> Looks reasonable, but does that work on all RISC-V variants?
From an RISC-V architectural perspective, yes.
Of course there might be a hardware bug in some given manufacturer's
implementation, but then again, that could happen on the other
architectures as well.
- Paul
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next prev parent reply other threads:[~2025-10-27 16:41 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-20 5:35 [PATCH v2] drm/ttm: add pgprot handling for RISC-V Icenowy Zheng
2025-10-27 7:56 ` Christian König
2025-10-27 16:41 ` Paul Walmsley [this message]
2025-10-28 8:20 ` Christian König
2025-10-27 17:10 ` Han Gao
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