Re: [PATCH v2] drm/ttm: add pgprot handling for RISC-V

From: "Christian König" <christian.koenig@amd.com>
To: Icenowy Zheng <uwu@icenowy.me>, Huang Rui <ray.huang@amd.com>,
	Matthew Auld <matthew.auld@intel.com>,
	Matthew Brost <matthew.brost@intel.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, Han Gao <rabenda.cn@gmail.com>,
	Vivian Wang <wangruikang@iscas.ac.cn>,
	Inochi Amaoto <inochiama@gmail.com>, Yao Zi <ziyao@disroot.org>
Subject: Re: [PATCH v2] drm/ttm: add pgprot handling for RISC-V
Date: Mon, 27 Oct 2025 08:56:58 +0100	[thread overview]
Message-ID: <dff6216d-b4a4-4d5d-89e3-e393dc018dec@amd.com> (raw)
In-Reply-To: <20251020053523.731353-1-uwu@icenowy.me>

On 10/20/25 07:35, Icenowy Zheng wrote:
> The RISC-V Svpbmt privileged extension provides support for overriding
> page memory coherency attributes, and, along with vendor extensions like
> Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
> 
> Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
> and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
> access attributes.
> 
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Han Gao <rabenda.cn@gmail.com>
> ---
> Changes in v2:
> - Added Han Gao's test tag.
> 
>  drivers/gpu/drm/ttm/ttm_module.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
> index b3fffe7b5062a..aa137ead5cc59 100644
> --- a/drivers/gpu/drm/ttm/ttm_module.c
> +++ b/drivers/gpu/drm/ttm/ttm_module.c
> @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
>  #endif /* CONFIG_UML */
>  #endif /* __i386__ || __x86_64__ */
>  #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
> -	defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
> +	defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
> +	defined(__riscv)

Looks reasonable, but does that work on all RISC-V variants?

And while at it maybe please fix the indentation, using a tab here is probably not very adequate. In other words make the defined() match the one on the first line.

Regards,
Christian.

>  	if (caching == ttm_write_combined)
>  		tmp = pgprot_writecombine(tmp);
>  	else

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